3D NAND Bonded Structure With Conductive Plate Grounding
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity while maintaining electrical characteristics and reliability, particularly in three-dimensionally arranged memory cells.
Innovation Solution
A semiconductor device design featuring a first substrate with circuit devices, a lower interconnection structure, and a second substrate with conductive patterns and gate electrodes stacked vertically, along with peripheral contact plugs, which simplifies the fabrication process and enhances electrical performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used to increase data storage capacity, then data storage capacity is improved, but fabrication complexity increases
Solution Approach 1:
The device is divided into a first semiconductor structure (peripheral circuit region) and a second semiconductor structure (memory cell region), which are bonded together. This segmentation allows independent fabrication and optimization of each region, simplifying the overall fabrication process while maintaining high storage capacity through the 3D vertical channel structures in the memory region.
Solution Approach 2:
The patent transitions from traditional 2D planar memory cell arrangements to 3D vertical channel structures with gate electrodes stacked in the vertical direction. This dimensional change increases storage capacity by utilizing vertical space, while the segmented fabrication approach makes this complex 3D structure manufacturable.
2Manufacturing precision
If conventional fabrication processes are used for three-dimensional memory cells, then manufacturing precision is maintained, but fabrication time increases
Solution Approach 1:
The first semiconductor structure (peripheral circuits) and second semiconductor structure (memory cells) are fabricated separately and independently before being bonded together. This preliminary action allows each structure to be optimized and completed in parallel, reducing total fabrication time while maintaining precision through dedicated fabrication processes for each region.
Solution Approach 2:
A bonding structure acts as an intermediary between the first and second semiconductor structures, enabling their separate fabrication and subsequent integration. This intermediary approach allows independent optimization of each region's fabrication process while ensuring precise alignment and connection through the bonding interface.
3Manufacturing precision
If alignment keys are included in the fabrication process, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent removes the need for separate alignment keys by integrating alignment functionality directly into the bonding structure. The bonding structure itself provides the reference for alignment between the first and second semiconductor structures, eliminating redundant components and simplifying the overall device structure while maintaining manufacturing precision.
Solution Approach 2:
The bonding structure serves multiple functions: it mechanically connects the first and second semiconductor structures, provides alignment reference during fabrication, and enables electrical or thermal coupling. This multi-functionality eliminates the need for separate alignment keys and reduces overall device complexity.
Data Source
AI summary
A semiconductor device includes: a first substrate; circuit devices disposed on the first substrate; a lower interconnection structure electrically connected to the circuit devices; a lower bonding structure connected to the lower interconnection structure; an upper bonding structure bonded to the lower bonding structure; an upper interconnection structure connected to the upper bonding structure; a second substrate disposed on the upper interconnection structure; a conductive plate disposed below the second substrate; gate electrodes disposed between the upper interconnection structure and the conductive plate and stacked in a vertical direction; channel structures penetrating through the gate electrodes; a plurality of conductive patterns, respectively disposed in a plurality of openings penetrating through the second substrate; and a peripheral contact plug extending in the vertical direction in an external region from the conductive plate and being connected to one of the plurality of conductive patterns.