3D NAND Memory Stacking With Bonded Peripheral Interconnects
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to size limitations, leading to increased costs and density constraints, which 3D memory architectures aim to address by vertically stacking memory arrays and peripheral devices to enhance density and performance.
Innovation Solution
The solution involves a semiconductor apparatus with a silicon substrate, peripheral devices, and a memory array, featuring interconnect layers, NAND strings, and a single crystalline silicon layer, allowing for vertical stacking and decoupling of peripheral and array device processing to improve thermal management and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but manufacturing cost increases and fabrication becomes challenging
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Memory arrays are formed as separate semiconductor structures that are vertically stacked above peripheral devices through wafer bonding, enabling increased memory density without further scaling of individual planar features and avoiding the fabrication challenges associated with continued planar scaling
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but manufacturing cost increases
Solution Approach 1:
By moving to 3D stacking architecture, the patent achieves higher memory density through vertical integration rather than continued planar scaling. This approach uses standard bonding and fabrication processes on separate wafers, avoiding the costly and complex process technology improvements required for further planar scaling
3Quantity of substance
If 3D memory architecture is implemented with vertical stacking, then memory density is improved, but thermal management becomes challenging
Solution Approach 1:
The patent segments the semiconductor device into separate functional components: peripheral devices on a first substrate and memory arrays on a second substrate. These are then bonded together through wafer bonding. This segmentation allows independent thermal management optimization for each component, with the peripheral device substrate serving as a thermal management structure for the memory arrays
Solution Approach 2:
The peripheral device substrate acts as an intermediary thermal management structure between the memory arrays and the external environment. The bonded interface provides thermal pathways, and the peripheral device substrate can be designed with specific thermal properties to manage heat dissipation from the vertically stacked memory arrays
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.