3D NAND Peripheral Circuit Bonding for Chip Area Reduction
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Solution Overview
Problem
The challenge in developing 3D memory devices is the increasing complexity and cost of scaling down peripheral circuits while maintaining high voltage requirements, which limits the reduction of chip size and memory density due to the need for more layers and increased metal routing, and the infeasibility of following the CMOS technology node trend for logic devices.
Innovation Solution
The solution involves stacking peripheral circuits in different planes vertically, separating high-voltage and low-voltage circuits, and using hybrid bonding and transfer bonding to reduce the planar area occupied by peripheral circuits, allowing for independent thermal budgets and the use of materials like copper for interconnects, while enabling the fabrication of memory cell arrays and peripheral circuits on different substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If peripheral circuits are scaled down to reduce chip size, then chip area is reduced, but manufacturing complexity and cost increase due to high voltage requirements and CMOS technology node limitations
Solution Approach 1:
The peripheral circuits are segmented into two separate semiconductor structures: one dedicated to high-voltage circuits and another to low-voltage circuits. This segmentation allows each structure to be optimized independently for its specific voltage requirements, avoiding the manufacturing complexity that would arise from integrating both high and low voltage circuits in a single scaled-down structure.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture. By stacking the high-voltage and low-voltage semiconductor structures vertically and bonding them together, the peripheral circuits are moved from a two-dimensional plane to a three-dimensional configuration. This dimensional change reduces the planar chip area while maintaining the necessary circuit functionality without the manufacturing complexity of further scaling.
2Reliability
If more layers and metal routing are added to maintain peripheral circuit functionality, then circuit performance is maintained, but chip size reduction is limited and fabrication complexity increases
Solution Approach 1:
By separating high-voltage and low-voltage circuits into distinct semiconductor structures, each structure can be fabricated with the appropriate number of layers and metal routing configurations needed for its specific voltage requirements. This segmentation avoids the need to add excessive layers and routing to a single unified structure, thereby maintaining circuit performance while reducing fabrication complexity.
3Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density approaches upper limit, but process technology becomes challenging and costly
Solution Approach 1:
The patent addresses the limitations of planar scaling by transitioning to a three-dimensional stacked memory architecture. Memory cells are arranged in multiple vertical layers stacked on top of each other, with peripheral circuits integrated in separate bonded structures. This vertical stacking dramatically increases memory density without requiring further planar scaling, thereby avoiding the process technology challenges and costs associated with continuing to shrink feature sizes.
4Area of stationary object
If high-voltage and low-voltage circuits are integrated in the same structure, then chip area is minimized, but thermal budgets and material requirements conflict
Solution Approach 1:
The peripheral circuits are divided into separate high-voltage and low-voltage semiconductor structures, each with its own optimized thermal budget and material stack. The high-voltage structure can use materials and processes suitable for high voltage operation, while the low-voltage structure can use different materials and processes optimized for low voltage. These separately optimized structures are then bonded together, achieving area minimization without the conflicts that would arise from trying to accommodate both voltage requirements in a single structure.
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit of the array of memory cells including a first transistor in contact with a first side of the second semiconductor layer, and a second peripheral circuit of the array of NAND memory strings including a second transistor in contact with a second side of the second semiconductor layer opposite to the first side.