3D NAND Memory Source Contact via Bottom-Up Etch
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Solution Overview
Problem
The challenge in fabricating 3D non-volatile memory devices lies in forming source contacts at the bottom of memory holes without damaging the interior linings, particularly due to the high aspect ratio of the memory holes, which can lead to damage to the pre-lined charge storage and channel films during top-down etching processes.
Innovation Solution
A bottom-up etch process is employed to create a lateral conduit path under the memory hole, allowing for the selective exposure and doping of the channel material at the bottom of the memory hole, reducing resistance and enabling the formation of low-resistance contacts without subjecting the interior linings to damaging etches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If top-down etching is used to create source contacts at the bottom of memory holes, then the source contact formation is achieved, but the interior linings of memory holes are damaged
Solution Approach 1:
The patent inverts the conventional top-down etching approach by implementing a bottom-up etching process. Source contacts are formed first at the bottom of memory holes, then etching proceeds upward through the channel material to expose contact regions. This reversal eliminates damage to the interior linings (charge storage and tunnel oxide layers) that would otherwise be exposed to damaging etchants during top-down processing.
Solution Approach 2:
The patent performs preliminary formation of source contacts at the bottom of memory holes before etching the channel material. By pre-forming the source contacts and then selectively removing channel material above them, the interior linings are protected from etching damage while still achieving the necessary contact formation.
2Manufacturing precision
If top-down etching is performed to expose channel material at the bottom, then contact exposure is achieved, but resistance increases due to lining damage
Solution Approach 1:
The patent reverses the etching direction to proceed from bottom to top, exposing channel material above the source contacts rather than etching down to expose contacts. This inversion ensures that the channel material exposure occurs without damaging the interior linings, thereby maintaining low contact resistance and high reliability.
Solution Approach 2:
The patent selectively extracts (removes) channel material above the source contacts through bottom-up etching, rather than removing interior linings to expose contacts. This extraction approach achieves the necessary contact exposure while preserving the integrity of the charge storage and tunnel oxide layers, ensuring low resistance and reliable contacts.
3Ease of manufacture
If high aspect ratio memory holes are etched top-down, then memory hole formation is achieved, but damage to charge storage and channel films occurs
Solution Approach 1:
The patent inverts the etching sequence by first forming source contacts at the bottom of memory holes, then etching upward to expose channel material. This bottom-up approach eliminates the need for damaging top-down etching through high aspect ratio holes, as the etching occurs later when the critical interior linings are already in place and protected.
Solution Approach 2:
The patent performs preliminary formation of source contacts and interior linings before performing any etching that would expose channel material. By establishing the protective interior linings first, subsequent etching operations can proceed without damaging the charge storage and channel films, even though the memory holes have high aspect ratios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents damage to the memory hole linings and allows for the creation of reliable, low-resistance contacts, enhancing the reliability and performance of the 3D stacked non-volatile memory devices by avoiding the need for top-down etching.
Implementation Method 1
A bottom-up etch process is employed to create a lateral conduit path under the memory hole, allowing for the selective exposure and doping of the channel material at the bottom of the memory hole
Implementation Method 2
allowing for the selective exposure and doping of the channel material at the bottom of the memory hole, reducing resistance and enabling the formation of low-resistance contacts
Data Source
AI summary
A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.