3D NAND BSG Cut Structure for Independent Sub-Array Control
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Solution Overview
Problem
Existing semiconductor technologies face challenges in forming bottom select gate (BSG) cut structures during the replacement of sacrificial layers with gate layers, leading to potential failures due to blocking by multiple BSG cut structures, which affects the integrity and functionality of vertical memory cell strings in 3D NAND flash memory devices.
Innovation Solution
The formation of BSG cut structures is achieved through backside processing after the replacement of sacrificial layers with gate layers, allowing for the creation of separate sub-arrays within the vertical memory cell strings, enabling individual control of bottom select transistors and improving operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple BSG cut structures are formed during replacement of sacrificial layers with gate layers, then sub-arrays can be separated and individually controlled, but blocking occurs leading to potential failures in vertical memory cell strings
Solution Approach 1:
The patent divides the vertical memory cell string into multiple sub-arrays by forming BSG cut structures that extend through the stack. These cut structures physically separate the memory cell string into first and second sub-arrays, enabling independent control of each sub-array through separate bit lines while maintaining structural integrity through proper design of the cut structures
Solution Approach 2:
The patent applies different properties to different regions by forming BSG cut structures with specific characteristics in certain locations. The cut structures are formed to extend through the stack at specific positions, creating localized separation zones that enable individual sub-array control without affecting the overall device functionality
2Manufacturing precision
If BSG cut structures are formed to enable sub-array separation, then threshold voltage control is improved, but over-erase issues may occur
Solution Approach 1:
By segmenting the memory cell string into separate sub-arrays through BSG cut structures, each sub-array can be independently controlled during erase operations. This prevents over-erase conditions that would occur if the entire string were treated as a single unit, as the erase voltage can be selectively applied only to the required sub-array
Solution Approach 2:
The patent enables independent control of threshold voltages for different sub-arrays by forming separate BSG cut structures. This allows different erase and program voltages to be applied to different sub-arrays, optimizing the voltage parameters for each sub-array's specific state and preventing over-erase conditions
Data Source
AI summary
Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of conductive layers and insulating layers stacked alternatingly in a first direction. The stack of conductive layers and insulating layers has a first side and a second side in the first direction. The semiconductor device then includes a semiconductor layer at the first side of the stack of conductive layers and insulating layers, and a first isolation structure extending through, in the first direction, the semiconductor layer and a subset of the stack of conductive layers and insulating layers. The subset of the stack of conductive layers and insulating layers includes a first conductive layer. The first isolation structure separates a first portion of the first conductive layer from a second portion of the first conductive layer.