3D NAND Buffer Barrier Layer Residual Metal Removal
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Solution Overview
Problem
Three-dimensional NAND flash memory devices face interference issues, particularly due to residual connections between memory cells, which affect their operation and storage density.
Innovation Solution
A three-dimensional non-volatile memory structure is developed, featuring a substrate with a charge storage structure, a stacked structure of insulating layers and gates, a buffer layer, and a barrier layer, where the buffer layer is discontinuous and the barrier layer has a low atomic concentration, reducing interferences by removing portions of the insulating layer between gates and stringers during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional NAND flash memory structure is used to increase storage density, then memory density and integration level are improved, but interference between memory cells due to residual connections increases
Solution Approach 1:
The patent removes portions of the insulating layer between adjacent memory cell strings to extract and eliminate residual connections (metal residues) that cause interference between memory cells. This extraction of harmful elements resolves the contradiction by maintaining high density while eliminating interference sources
Solution Approach 2:
The patent applies different properties to different regions: the insulating layer is removed locally between adjacent strings where interference occurs, while maintaining its insulating properties in other critical areas. This localized modification eliminates interference without compromising overall device functionality
2Reliability
If insulating layers are removed between gates to eliminate metal residues, then interference between gates is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary patterning of the insulating layer during the formation of the charge storage structure, creating recessed regions between adjacent strings before gate formation. This preliminary action simplifies subsequent processing by pre-positioning the insulating layer removal zones, thereby reducing overall manufacturing complexity while ensuring complete elimination of metal residues
Solution Approach 2:
The patent combines the insulating layer removal step with existing manufacturing processes, integrating the elimination of metal residues into the standard fabrication sequence rather than adding separate complex steps. This merging approach reduces manufacturing complexity while achieving the reliability improvement
Data Source
AI summary
A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.