3D NAND Pillar Patterning With Buttress Supports for Uniform Hard Masks
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Solution Overview
Problem
The challenge in fabricating 3D NAND memory devices lies in achieving uniformity and evenness of patterned feature sizes and shapes on the hard mask layer using single exposure lithography techniques, which results in uneven memory pillars, necessitating additional features adjacent to the memory pillar hard mask to improve patterning uniformity.
Innovation Solution
The application of a Litho-Etch-Litho-Etch-Litho-Etch (LELELE) technique using striped masks to pattern hexagonal features on the hard mask layer, forming a grid of supporting buttress pillars aligned with NAND memory pillars through a stack of lattice layers, providing structural support and improving patterning uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single exposure lithography technique is used to pattern hard mask, then manufacturing process is simple, but patterning uniformity and feature shape evenness deteriorate
Solution Approach 1:
The patent divides the single lithography exposure into three separate exposure steps (first, second, and third exposures) with different stripe patterns. Each exposure creates a specific set of features, and the combination of all three exposures achieves the desired uniform patterning across the entire hard mask layer, resolving the contradiction between process simplicity and patterning uniformity.
Solution Approach 2:
The patent introduces a temporal dimension by performing three sequential lithography exposures instead of a single exposure. The stripe patterns are applied in different orientations (first horizontal, second angled right, third angled left) across different exposure steps, transforming a two-dimensional patterning problem into a three-dimensional solution space that achieves superior uniformity.
2Manufacturing precision
If feature density is increased in support region, then hard mask patterning uniformity improves, but device complexity increases
Solution Approach 1:
The patent employs asymmetric stripe patterns where the first, second, and third exposures create different stripe orientations and densities in different regions of the hard mask. The support region receives enhanced feature density through specific stripe intersections, while the core region maintains appropriate feature spacing, achieving uniform patterning without symmetric complexity throughout the entire structure.
Solution Approach 2:
The three stripe technique applies different exposure patterns to different regions of the hard mask layer. The support region receives a higher density of intersecting stripes from the three exposures, creating local feature density enhancement where needed, while the core region maintains appropriate patterning without unnecessary complexity.
3Manufacturing precision
If additional features are added adjacent to memory pillar hard mask, then patterning uniformity improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of memory pillar features and support region features into a single integrated three-exposure lithography process. Instead of separately patterning memory pillars and then adding support features, all features are created simultaneously through the three stripe exposures, achieving uniform patterning without additional manufacturing steps.
Solution Approach 2:
The three stripe lithography technique serves multiple functions simultaneously: it patterns the memory pillar hard masks, creates the support region features, and enhances overall patterning uniformity all in one process sequence. This multi-functional approach eliminates the need for separate process steps to add support features.
Data Source
AI summary
A three-dimensional (3D) memory device including a stack of alternating supporting lattice layers and dielectric layers on a substrate, a plurality of memory pillars vertically penetrating the stack, each of the plurality of memory pillars including a plurality of vertically connected replacement gate (RG) memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first polygon shape having at least six sides in a horizontal plane parallel to the supporting lattice layers, and a plurality of supporting buttress (SBT) pillars exclusive of any memory cells that are located at outside ends of the plurality of memory pillars and that vertically penetrate the stack, wherein the plurality of memory pillars and the plurality of SBT pillars are laterally connected by the supporting lattice layers.