3D NAND Memory Stack Etching with Protective Cap and Spacer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming monolithic vertical NAND strings with minimal damage to semiconductor channel layers and memory films during etching processes, leading to reduced performance and reliability.
Innovation Solution
A method involving alternating stacks of insulating and sacrificial layers, an insulating cap layer, and annular spacers is employed to form memory stack structures with controlled etching processes, reducing damage and enhancing the integrity of semiconductor channels and memory films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sequential etching of multilayer stacks is used to form vertical NAND strings, then monolithic three-dimensional memory devices can be manufactured, but damage occurs to semiconductor channel layers and memory films during the etching process
Solution Approach 1:
The patent applies preliminary action by forming protective structures (such as sacrificial layers or protective coatings) on the semiconductor channel layers and memory films before the etching process begins. These protective structures are prepared in advance to prevent damage during subsequent etching operations, allowing precise etching of the vertical NAND strings while preserving the integrity of sensitive layers.
Solution Approach 2:
The patent introduces intermediary protective layers or sacrificial materials that act as mediators between the etching process and the sensitive semiconductor channel layers and memory films. These intermediary structures absorb or deflect the harmful effects of etching, enabling precise pattern transfer while protecting the underlying sensitive layers from damage.
2Productivity
If conventional etching processes are used to form vertical NAND strings, then memory devices can be manufactured, but device performance and reliability are reduced due to layer damage
Solution Approach 1:
The patent converts the potentially harmful etching process into a beneficial operation by using controlled etching methods that selectively remove sacrificial or protective layers while preserving the semiconductor channel layers and memory films. The etching process, which could cause damage, is transformed into a precise tool for forming vertical NAND strings with enhanced device performance and reliability through careful control of etching parameters and sequence.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A monolithic three-dimensional memory device is disclosed herein. The device comprises a first alternating stack of first insulating layers 132 and first electrically conductive layers 146 located over a top surface of a substrate 10, an insulating cap layer 170A overlying the first alternating stack (132, 146), a second alternating stack of second insulating layers 232 and second electrically conductive layers 246 overlying the insulating cap layer 170A, and a memory stack structure 55 extending through the second alternating stack (232, 246), the insulating cap layer 170A and the first alternating stack (132, 146). The memory stack structure 55 comprises a semiconductor channel 60 and a memory film 50 including a plurality of charge storage regions. The insulating cap layer 170A comprises a first concave surface having a first radius of curvature R1, laterally surrounding the memory stack structure 55, and adjoined to an upper periphery of a substantially vertical sidewall of the memory stack structure 55, and the insulating cap layer 170A comprises a second concave surface having a second radius of curvature R2 that is greater than the first radius of curvature R1, laterally surrounding the memory stack structure 55, and adjoined to an upper periphery of the first concave surface.