3D NAND Electron Capture Layer Structure for Data Retention
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Solution Overview
Problem
Charge diffusion in the electron capture layer of a 3D NAND flash memory device after a programming operation leads to a decrease in threshold voltage, resulting in poorer data retention capability.
Innovation Solution
The fabrication method involves forming the electron capture layer close to the channel structure, using etching techniques with photosensitive layers as masks to retain dielectric layers at specific surfaces, thereby preventing charge diffusion and maintaining threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge is stored in the electron capture layer after programming operation, then data is stored in the memory cell, but charge diffuses over time leading to threshold voltage decrease and poor data retention
Solution Approach 1:
The patent segments the electron capture layer into multiple distinct layers (first electron capture layer and second electron capture layer) with different materials and positions. This segmentation allows each layer to serve specific functions: the first layer captures charges during programming while the second layer prevents diffusion, thereby resolving the contradiction between data storage and charge stability.
Solution Approach 2:
The patent introduces an intermediary structure (the second electron capture layer made of nitride material) between the charge storage region and the surrounding environment. This intermediary layer acts as a barrier that prevents charge diffusion while allowing the first electron capture layer to maintain its charge storage function, thus improving data retention without compromising storage capability.
2Reliability
If conventional fabrication methods are used to form electron capture layer, then manufacturing is simpler, but charge diffusion occurs leading to threshold voltage decrease
Solution Approach 1:
The patent applies preliminary action by forming the first electron capture layer (oxide material) during the standard programming process, then subsequently forming the second electron capture layer (nitride material) in a separate fabrication step. This preliminary formation of the charge capture structure followed by the protective barrier layer allows the device to achieve improved data retention while maintaining compatibility with existing fabrication workflows.
Solution Approach 2:
The patent applies local quality by using different materials (oxide for first layer, nitride for second layer) at different positions within the electron capture structure. The first layer uses oxide material optimized for charge capture, while the second layer uses nitride material optimized for preventing diffusion. This localized material differentiation resolves the contradiction between simple fabrication and improved reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data retention capability by avoiding charge diffusion in the electron capture layer, thus maintaining the threshold voltage and improving memory cell performance.
Implementation Method 1
When programming the memory cell, the charges flow from the substrate into an electron capture layer of a memory cell by utilizing the tunnel effect
Data Source
AI summary
A 3D NAND flash memory device and fabricating method thereof, comprises: First, a semiconductor substrate layer is provided, wherein cell isolation structures, channel structures and source lead-out spaces are formed on the semiconductor substrate layer, with the cell isolation structures including cell isolation layers and memory cell-occupied spaces. First dielectric layers and second dielectric layers are sequentially deposited, the first dielectric layer covering at least an exposed surface of the cell isolation structure. The second dielectric layers are then etched to remove all of the second dielectric layers on the side surface and at least part of the second dielectric layers on the second surface, and all of the second dielectric layers on the first surface is retained, with the remaining second dielectric layer forming at least one electron capture layer for memory cell structures. The memory cell structures and electrode structures for the flash memory device are finally fabricated.