3D NAND Programming with Cell Classification to Cut Verify Loops
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Solution Overview
Problem
The total number of programming pulses and verify loop counts required for incremental step pulse programming (ISPP) in 3D NAND systems limits programming speed, and variations in fabrication processes lead to differences in programming speed among memory cells, with the slowest cell determining the minimum number of pulses needed, thus necessitating improved programming operations to enhance writing speed.
Innovation Solution
A method involving applying multiple voltage levels to bit lines and word lines based on the classification of memory cells determined through verify operations, including applying a first voltage greater than zero, a second voltage equal to the first voltage for one classification, and a third voltage greater than the second voltage for another classification, to optimize programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If incremental step pulse programming (ISPP) is applied to program memory cells, then programming precision is improved, but the total number of programming pulses and verify loop counts increases, limiting programming speed
Solution Approach 1:
The patent segments the memory cell array into multiple sub-arrays and divides the programming operation into parallel sub-operations. Each sub-array is programmed independently with its own verify loops, allowing simultaneous execution of multiple programming sequences. This segmentation reduces the total number of sequential verify loops needed while maintaining ISPP precision, thereby improving programming speed without sacrificing accuracy.
2Manufacturing precision
If the programming voltage is incrementally increased by adding step pulses to achieve required voltage, then programming precision is improved, but the time required for programming operations increases
Solution Approach 1:
The patent applies preliminary classification to memory cells based on their fabrication process variations before initiating the full ISPP sequence. Cells are grouped into categories (e.g., fast-programming and slow-programming cells) based on initial characteristics. This preliminary action allows the system to pre-determine appropriate programming parameters for each group, reducing the number of iterative verify loops needed and thereby decreasing programming time while maintaining voltage precision.
Solution Approach 2:
The patent dynamically adjusts programming parameters based on real-time verify results and cell classification. Instead of using fixed step pulse intervals for all cells, the system adapts the programming voltage steps and verify timing based on the specific characteristics of each cell group. This dynamic adjustment optimizes the balance between voltage precision and programming speed, reducing unnecessary verify loops for cells that reach target voltage faster.
3Manufacturing precision
If verify operations are performed to determine threshold voltage and compare with voltage range, then programming precision is improved, but the number of verify loop counts increases, limiting programming speed
Solution Approach 1:
The patent segments the verify operation into parallel sub-operations across multiple sub-arrays. Instead of sequentially verifying all cells in one large array, the system divides cells into smaller groups that can be verified simultaneously. Each sub-array undergoes its own verify loop independently, reducing the total number of sequential verify cycles required while maintaining threshold voltage precision through consistent verification criteria applied to each segment.
Solution Approach 2:
The patent applies partial verify actions by performing simplified or reduced verify operations on certain cell groups based on their classification. For example, fast-programming cells may undergo fewer verify loops or less stringent verification compared to slow-programming cells. This partial action approach maintains adequate threshold voltage precision for all cells while reducing the overall number of verify loops, thereby improving programming throughput.
Data Source
AI summary
The present disclosure provides a method for performing a programming operation on a memory cell connected to a bit line and controlled by a word line. The method includes applying a first programming voltage signal to the word line to program the memory cell into a first state, applying a first voltage to the bit line, performing a verify operation when the memory cell is in a second state, determining a classification of the memory cell based on the verify operation, applying a second voltage to the bit line based on the determined classification, applying a second programming voltage signal to the word line to program the memory cell into the first state, applying a third voltage to the bit line, applying a third programming voltage signal to the word line to program the memory cell into the first state, and applying a fourth voltage to the bit line.