3D NAND Cell Pillar and Active Body Layout for Higher Density
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Solution Overview
Problem
Conventional microelectronic device configurations, particularly in memory devices like 3D NAND Flash memory, face challenges in achieving high integration density, compact design, and improved performance due to processing limitations and complex manufacturing processes that hinder reductions in size and enhance performance metrics such as speed and power consumption.
Innovation Solution
The method involves forming a microelectronic device structure with a base structure, memory array region, conductive material, isolation materials, lateral contact structures, and vertically extending cell pillar structures, along with conductive routing tiers and isolation materials to optimize the configuration and performance of control logic devices, allowing for improved integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory device configurations are used, then manufacturing processes are established, but integration density is limited and device size cannot be reduced
Solution Approach 1:
The patent transitions from planar (2D) memory array arrangements to three-dimensional (3D) vertical stack structures, where memory cells are stacked vertically above control logic devices. This dimensional change enables higher integration density by utilizing the vertical space above the control logic region, effectively multiplying the number of memory cells per unit area without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent merges the control logic region and memory array region into a single integrated structure where control logic devices and memory cells share the same semiconductor substrate and undergo coordinated formation processes. This merging eliminates the need for separate fabrication processes for control logic and memory arrays, reducing overall manufacturing complexity while achieving high integration density.
2Reliability
If processing conditions are optimized for memory array formation, then memory cell performance is improved, but control logic device configurations are limited
Solution Approach 1:
The patent forms control logic devices first in the control logic region, then uses these pre-formed control logic devices as a foundation for subsequent memory cell formation. The control logic devices are prepared with their transistors, interconnects, and isolation structures before the memory stack is built above them. This preliminary action allows the control logic to be optimized independently while still enabling high-performance memory cells to be formed afterward using the same processed substrate.
3Area of moving object
If device size is reduced, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent reduces the horizontal footprint of the memory device by stacking memory cells vertically above the control logic region rather than extending the memory array laterally. This vertical stacking approach maintains high integration density while using standard planar fabrication processes, avoiding the need for complex 3D manufacturing techniques that would increase process complexity.
4Quantity of substance
If conventional planar arrangements are used, then manufacturing is simplified, but integration density is limited
Solution Approach 1:
The patent implements a vertical stack structure where memory cells are arranged in tiers above the control logic region, with each tier containing multiple memory cells stacked vertically. This 3D architecture uses alternating conductive and insulating material layers to form the memory cell structure, enabling high memory cell density while maintaining compatibility with standard semiconductor fabrication processes through sequential deposition and patterning steps.
Data Source
AI summary
A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.