3D NAND Memory Structure With Separated Channel and Low-Resistance Regions
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Solution Overview
Problem
The challenge in fabricating a three-dimensional NAND memory element using a metal oxide for a semiconductor layer is the separate formation of a channel formation region and a low-resistance region.
Innovation Solution
A semiconductor device is designed with specific insulators and conductors to form separate channel formation and low-resistance regions, utilizing a metal oxide semiconductor layer, where the low-resistance region is formed by accumulating charge in a specific insulator upon potential supply to the conductor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a metal oxide semiconductor layer is used to form both channel formation region and low-resistance region, then the semiconductor layer can be simplified, but it becomes difficult to separately form the channel formation region and low-resistance region with distinct carrier concentrations
Solution Approach 1:
The patent divides the semiconductor layer into distinct regions: a channel formation region with lower carrier concentration and low-resistance regions with higher carrier concentration. This segmentation allows each region to be optimized independently for its specific function while using the same metal oxide material system, resolving the contradiction between structural simplification and manufacturing precision.
Solution Approach 2:
The patent applies local quality by creating regions with different carrier concentrations within the metal oxide semiconductor layer. The channel formation region maintains lower carrier concentration for proper transistor operation, while the low-resistance regions have higher carrier concentration for reduced contact resistance, allowing each local area to have the properties needed for its specific function.
2Reliability
If the channel formation region and low-resistance region are formed separately in a metal oxide semiconductor layer, then distinct functional regions can be achieved, but the fabrication process becomes more complex
Solution Approach 1:
The patent employs preliminary action by forming the insulator layer structure (including the fourth insulator) before forming the semiconductor layer. This preliminary structure is then used as a template or guide during semiconductor layer formation, allowing the channel formation region and low-resistance region to be created with precise spatial control through subsequent processing steps such as selective deposition or doping.
Solution Approach 2:
The patent uses an insulator layer (particularly the fourth insulator) as an intermediary element that facilitates the separate formation of the channel formation region and low-resistance region. This intermediary structure enables controlled interaction between processing steps and the semiconductor material, allowing precise regional differentiation while maintaining overall process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a semiconductor device with a metal oxide semiconductor layer, achieving a memory device with large data capacity and high reliability by effectively separating the channel formation and low-resistance regions.
Implementation Method 1
the low-resistance region is formed by accumulating charge in a specific insulator upon potential supply to the conductor
Data Source
AI summary
An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.