3D NAND Metal Oxide Channel Structure With Low-Resistance Region
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Solution Overview
Problem
The challenge in fabricating three-dimensional NAND memory elements using a metal oxide semiconductor layer is the separate formation of a channel formation region and a low-resistance region, which is crucial for achieving high memory capacity and reliability.
Innovation Solution
A semiconductor device configuration involving multiple insulators and conductors is employed, where a low-resistance region is formed at the interface with a specific insulator, and a channel formation region is defined in a region overlapping a conductor, utilizing a metal oxide with a conductive compound that includes components from both the metal oxide and the insulator, enabling effective charge accumulation and carrier transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a metal oxide semiconductor layer is used to increase memory capacity, then the memory capacity is improved, but the separate formation of channel formation region and low-resistance region becomes difficult
Solution Approach 1:
The patent applies local quality by creating distinct regions within the metal oxide semiconductor layer with different properties. The channel formation region is formed with specific metal oxide characteristics to enable carrier transport, while the low-resistance region is formed with different metal oxide characteristics (such as higher carrier concentration) to reduce resistance. This is achieved through selective doping, selective removal of elements, or selective formation conditions in different spatial regions of the semiconductor layer, allowing both regions to coexist and function optimally within the same metal oxide-based structure.
2Quantity of substance
If a metal oxide semiconductor layer is used, then the memory capacity is improved, but the fabrication complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the metal oxide semiconductor layer into functionally distinct segments: a channel formation region and a low-resistance region. This segmentation allows each region to be optimized independently for its specific function while maintaining the overall metal oxide semiconductor structure. The segmentation can be achieved through selective processing steps applied to different regions, such as selective doping, selective element removal, or selective annealing, thereby managing fabrication complexity through modular regional optimization rather than treating the entire layer uniformly.
3Reliability
If separate formation of channel and low-resistance regions is achieved, then the reliability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by preparing the metal oxide semiconductor layer in advance to facilitate subsequent regional differentiation. This may involve initial uniform doping, pre-formed structural features, or preliminary thermal treatment that creates a baseline structure from which the channel formation region and low-resistance region can be selectively developed. The preliminary actions set up the conditions that make later regional differentiation easier and more precise, reducing the precision burden on subsequent steps by having the material already primed for selective modification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the separate and reliable formation of channel and low-resistance regions, enhancing memory capacity and reducing power consumption by minimizing leakage current, thus achieving a highly reliable memory device.
Implementation Method 1
utilizing a metal oxide with a conductive compound that includes components from both the metal oxide and the insulator, enabling effective charge accumulation and carrier transport
Data Source
AI summary
An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.