3D NAND Memory Channel Width Expansion

The patent transitions from planar 2D memory cell layout to a 3D vertical architecture where memory cells are stacked in multiple layers. Word lines extend in the first direction (X-axis) while bit lines extend in the second direction (Y-axis), creating a three-dimensional cell structure that increases storage density without proportionally reducing cell current. The vertical stacking of multiple memory cell layers along the third direction (Z-axis) allows higher storage capacity while maintaining adequate current flow through each cell.

The memory device is divided into multiple independent memory cell layers stacked vertically, with each layer containing complete sets of word lines, bit lines, and memory cells. This segmentation allows the total storage capacity to be distributed across multiple layers, effectively increasing overall capacity while each individual layer maintains sufficient cell current for reliable operation. The segmented structure also enables independent optimization of current paths in each layer.

The patent introduces a third vertical dimension for channel formation, creating vertically extending channels that connect source and drain regions through multiple stacked memory cell layers. This 3D channel architecture compensates for the reduced horizontal channel width by providing additional vertical channel length, thereby maintaining adequate total channel area and reducing resistance while achieving high storage density through vertical stacking.

The channel structure utilizes composite material layers including semiconductor layers (such as silicon germanium or indium gallium phosphide) with different bandgap properties, combined with charge storage films and tunnel insulating films. These composite structures optimize carrier transport through the channel while enabling miniaturization, achieving both high storage density and low resistance through material engineering.