3D NAND Memory Erasing Sequence for Charge-Loss Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The variation in charge losses among memory cells in a memory device leads to differences in read windows, causing errors in data reading and Error-Correcting operations, particularly in multi-level cells like TLC applications.
Innovation Solution
A memory device and operating method that involves a first erasing operation followed by a second erasing operation with a lower voltage to adjust charge losses, where the second erasing voltage is applied to specific parts of memory cells after programming, reducing the difference in charge losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single erasing operation is performed on memory cell strings, then the erasing process is simple and fast, but the charge losses of memory cells vary significantly leading to read errors
Solution Approach 1:
The erasing operation is divided into two distinct segments: a first erasing operation that applies a first erasing voltage to erase memory cell strings, and a second erasing operation that applies a second erasing voltage (lower than the first) to at least one part of memory cells in the same strings. This segmentation allows different portions of memory cells to receive differentiated erasing treatment, reducing charge loss variation and improving read accuracy without requiring completely new hardware
Solution Approach 2:
The second erasing operation is applied selectively to at least one part of memory cells in each string rather than uniformly to all cells. This local quality approach targets specific cells that require additional erasing to achieve uniform charge loss characteristics, thereby improving overall reliability while minimizing the impact on device complexity
2Reliability
If a first erasing voltage is applied to erase memory cell strings, then erasing is effective, but charge losses of memory cells become uneven affecting read windows
Solution Approach 1:
The first erasing operation is performed as a preliminary step before programming, ensuring that all memory cell strings are properly erased with a high first erasing voltage. This preliminary action creates a uniform starting state, and the subsequent second erasing operation fine-tunes the charge loss uniformity after programming, thereby improving charge loss uniformity without significantly extending the critical programming time
3Quantity of substance
If multi-level cells are used to increase storage capacity, then storage density improves, but charge loss variation causes errors in Error-Correcting operations
Solution Approach 1:
The invention changes the voltage parameter by applying two different erasing voltages: a first erasing voltage for the initial erasing operation and a second erasing voltage (lower than the first) for the second erasing operation on specific memory cells. This parameter change allows precise control over charge loss characteristics in multi-level cells, improving Error-Correcting operation accuracy while maintaining the high storage capacity enabled by multi-level cell technology
Data Source
AI summary
A memory device and an operating method for the memory device are provided. The memory device includes a memory array and a control circuit. The memory array includes memory blocks. Each of the memory blocks is, for example a three-dimensional NAND flash memory block. The memory device provides a storage media with high-performance and high-capacity. The control circuit provides a first erasing voltage to perform a first erasing operation on target memory cell strings of a selected memory block in the memory blocks, performs a programming operation on the target memory cell strings after the first erasing operation, and provides a second erasing voltage to perform a second erasing operation on at least one part of memory cells of each of the target memory cell strings after the programming operation. The second erasing voltage is lower than the first erasing voltage.