3D NAND Memory Charge Pump Noise Control
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in reducing costs while increasing storage capacity, as three-dimensional memory structures require costly lithography steps and can lead to noise interference from power supply circuits, causing write and read errors.
Innovation Solution
The semiconductor memory device employs a control method where charge pumps are driven only when not performing write or read operations, and are strategically positioned below unselected cell array blocks to minimize noise interference, allowing for efficient voltage supply and reduced error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If charge pumps are embedded below the cell array to reduce area, then chip area is reduced, but noise interference increases causing write and read errors
Solution Approach 1:
The cell array is divided into multiple blocks, and charge pumps are selectively activated based on which block is being accessed. When a specific block is selected for read/write operations, only the charge pumps corresponding to unselected blocks remain active, segmenting the noise sources spatially and temporally to prevent interference with the selected block's signal integrity.
Solution Approach 2:
The charge pumps are designed with dynamic control capability, allowing their activation state to change based on the selected block. The control circuit dynamically adjusts which charge pumps are active during read/write operations, transitioning between different operational states to minimize noise while maintaining voltage supply functionality.
2Quantity of substance
If three-dimensional memory stacking is used to increase storage capacity, then storage capacity increases, but manufacturing cost increases due to multiple lithography steps
Solution Approach 1:
The patent transitions from two-dimensional planar memory architecture to three-dimensional stacked architecture, where memory cells are arranged in multiple layers vertically. This dimensional change allows increased storage capacity within the same chip footprint, achieving higher density without proportionally increasing lithography complexity for each additional layer.
Solution Approach 2:
The charge pumps serve multiple functions: they provide voltage boosting for memory operations and are strategically positioned to act as noise isolation elements. By embedding power supply circuits within the three-dimensional structure rather than adding separate components, the design achieves multi-functionality that reduces overall manufacturing complexity and cost.
3Reliability
If charge pumps are activated continuously to ensure voltage supply, then power supply reliability is improved, but noise interference increases causing operational errors
Solution Approach 1:
Instead of continuous activation, charge pumps are activated periodically and selectively based on operational requirements. The control circuit determines which charge pumps should be active at any given time based on the selected block, creating a periodic activation pattern that maintains power supply reliability while minimizing noise generation during read/write operations.
Solution Approach 2:
Different charge pumps have different activation states based on their spatial relationship to the selected block. Charge pumps associated with unselected blocks remain active and provide voltage supply, while charge pumps near the selected block are deactivated to minimize noise. This local differentiation of activation quality ensures power reliability where needed while reducing noise where critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces noise interference and suppresses write and read errors by controlling the activation of charge pumps, thereby enhancing the operational efficiency and reducing the overall chip area.
Implementation Method 1
a voltage generation circuit (charge pump) is arranged below each block
Implementation Method 2
driven charge pumps which do not give noise to the signal
Implementation Method 3
two adjacent silicon pillars form one NAND string... the lower ends of the two adjacent silicon pillars are connected by a transistor called a pipe
Data Source
AI summary
A semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target.