3D NAND Channel Hole Structure for Charge Retention
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, traditional fabrication techniques become challenging and costly, necessitating a shift to three-dimensional (3D) memory architectures to enhance memory density.
Innovation Solution
A method for forming a 3D NAND memory device involves creating an alternating layer stack on a substrate, forming channel holes, and constructing a functional layer with a storage layer having an uneven surface to inhibit charge spreading, which includes a barrier layer for blocking electronic charge outflow and a tunneling layer for charge tunneling, along with a channel layer and filling structure to cover and fill the holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by forming vertical channel holes through alternating layer stacks. This dimensional change allows memory density to increase vertically rather than requiring continuous lateral scaling, thereby avoiding the manufacturing complexity and cost associated with further planar miniaturization.
2Manufacturing precision
If feature sizes of planar memory cells approach lower limit, then memory density approaches upper limit, but fabrication techniques become challenging and costly
Solution Approach 1:
Instead of continuing to reduce feature sizes in the planar dimension, the patent moves to vertical stacking with channel holes penetrating through alternating layer stacks. This approach achieves higher memory density without requiring further reduction of lateral feature sizes, thereby maintaining fabrication ease while approaching the upper limit of memory density.
3Reliability
If functional layer with uneven surface is formed to inhibit charge spreading, then data retention performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent forms a functional layer with an uneven surface where the thickness varies locally to inhibit charge spreading. By creating regions of different thickness in the functional layer (particularly in the charge trapping layer), the structure achieves better charge confinement and data retention performance without requiring entirely new manufacturing processes, thus balancing reliability improvement with acceptable process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves data retention performance and cell operation speed by reducing charge lateral spreading and vertical charge loss, thereby overcoming the limitations of planar memory cells.
Implementation Method 1
forming a barrier layer on the sidewall of each channel hole for blocking an outflow of the electronic charges during operation
Implementation Method 2
forming a tunneling layer on a surface of the storage layer for tunneling electronic charges during operation
Implementation Method 3
forming an alternating layer stack on a substrate... forming a plurality of conductive/dielectric layer pairs on the substrate, each conductive/dielectric layer pair comprising a conductive layer and a dielectric layer
Data Source
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AI summary
A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating layer stack on a substrate; forming a plurality of channel holes in the alternating layer stack, each penetrating vertically through the alternating layer stack; forming a functional layer including a storage layer on a sidewall of each channel hole, wherein the storage layer has an uneven surface; forming a channel layer to cover the functional layer in each channel hole; and forming a filling structure to cover the channel layer and fill each channel hole.