3D NAND Stack Insulative Structure for Lower Charge Trapping
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Solution Overview
Problem
Existing 3D-NAND flash memory devices face issues with charge trapping in horizontal inter-poly dielectric (IPD) materials, leading to degraded cell program-erase cycling and unreliable threshold voltage, due to the presence of oxide-nitride-oxide (ONO) materials, which complicates fabrication and increases critical dimensions.
Innovation Solution
A fabrication process that forms floating gates with a height equal to adjacent control gates by using oxide materials with different densities, allowing selective etching to control the height and profile of control gate recesses, thereby minimizing charge trapping and maintaining critical dimensions without additional complex steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide-nitride-oxide (ONO) materials are used as inter-poly dielectric, then charge blocking function is provided, but charge trapping occurs leading to degraded program-erase cycling and unreliable threshold voltage
Solution Approach 1:
The patent removes the nitride layer from the inter-poly dielectric structure, extracting the harmful charge-trapping component while retaining the oxide layers that provide electrical isolation. This leaves a simplified oxide-oxide structure that eliminates the charge trapping issue while maintaining the necessary dielectric function.
Solution Approach 2:
The patent converts the harmful charge-trapping property of nitride material into a beneficial simplification by removing it entirely. The resulting oxide-oxide structure provides both charge blocking and electrical isolation without the detrimental effects, turning the problematic multi-layer structure into a simpler, more reliable configuration.
2Manufacturing precision
If floating gates are made shorter than control gates, then charge blocking is achieved, but fabrication complexity increases and critical dimensions are compromised
Solution Approach 1:
The patent merges the floating gate height with the control gate height, making them substantially equal. This eliminates the need for separate etching steps to create recesses for shorter floating gates, simplifying the fabrication process while maintaining adequate charge blocking through the oxide-oxide dielectric structure.
Solution Approach 2:
The patent segments the dielectric function from the gate structure geometry, placing charge blocking oxide layers horizontally between gates rather than relying on vertical gate height differences. This allows floating gates to be the same height as control gates without compromising charge blocking functionality.
3Manufacturing precision
If oxide materials with different densities are used, then selective etching enables precise control of control gate recesses, but material selection and process control become more challenging
Solution Approach 1:
The patent applies local quality by using oxide materials with different densities at different locations in the dielectric stack. The first oxide layer has different etch characteristics than the second oxide layer, allowing selective removal of the first oxide to create precisely controlled recesses for control gates while leaving the second oxide intact for charge blocking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enhances channel conductance modulation, reduces cell noise, and improves reliability by aligning floating and control gates while maintaining device performance and simplifying the fabrication process.
Implementation Method 1
using oxide materials with different densities, allowing selective etching to control the height and profile of control gate recesses
Data Source
AI summary
Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.