3D NAND Flash Memory Chip Area Reduction via Vertical Stacking
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Solution Overview
Problem
Current semiconductor storage devices face challenges in reducing chip area due to high integration, which leads to increased space requirements and inefficiencies in memory cell transistor placement.
Innovation Solution
The semiconductor storage device employs a three-dimensionally stacked NAND-type flash memory configuration with memory cell transistors stacked above a semiconductor substrate, utilizing a specific arrangement of wiring layers, insulation layers, and charge storage layers to reduce chip area by oxidizing charge storage layers between memory cell transistors, allowing for closer pitch and reduced integration-related area increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell transistors are stacked three-dimensionally to increase storage capacity, then storage density is improved, but chip area increases due to integration requirements
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking of memory cell transistors. Multiple memory cell transistors are stacked above a single bit line contact, utilizing the vertical dimension to increase storage capacity without proportionally increasing chip area. This dimensional change allows higher integration while controlling footprint.
Solution Approach 2:
The patent implements a nested structure where charge storage layers are positioned within and between memory cell transistors in the vertical stack. The charge storage layers are embedded in the insulating film between adjacent memory cell transistors, creating a nested arrangement that maximizes space utilization and reduces required chip area.
2Area of stationary object
If memory cell transistors are placed closer together to reduce chip area, then chip area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the charge storage function into multiple discrete charge storage layers positioned at different vertical levels. These layers are formed between adjacent memory cell transistors in the stack, segmenting the storage function across multiple layers rather than requiring high precision in a single plane. This segmentation relaxes pitch precision requirements while maintaining compact area.
3Reliability
If more insulation layers are added between wiring layers to support three-dimensional stacking, then device reliability is improved, but device complexity increases
Solution Approach 1:
The insulating film in the patent serves multiple functions simultaneously: it acts as electrical insulation between adjacent memory cell transistors, provides a matrix for embedding charge storage layers, and enables vertical stacking of memory cell transistors above bit line contacts. This multi-functionality reduces the need for separate dedicated insulation layers, thereby reducing structural complexity while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the chip area by allowing for closer placement of memory cell transistors, preventing area increases associated with high integration and enhancing storage density.
Implementation Method 1
oxidizing charge storage layers between memory cell transistors
Data Source
AI summary
A semiconductor storage device includes a semiconductor substrate and a plurality of first wiring layers stacked above the semiconductor substrate in a first direction orthogonal to the semiconductor substrate, and extending in a second direction intersecting the first direction and parallel to the semiconductor substrate. The device further includes a first memory pillar including a semiconductor layer and a first insulation layer extending in the first direction, the first insulation layer provided between the plurality of first wiring layers and the semiconductor layer so as to contact the semiconductor layer, and charge storage layers provided respectively between the plurality of first wiring layers and the first insulation layer. One or more of the charge storage layers is in contact with the first insulation layer. A plurality of second insulation layers is provided between each of the plurality of first wiring layers and each of the charge storage layers.