3D NAND Memory Comb Structure Ion Implantation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of storage memory cells in planar NAND flash memory is limited by device critical dimensions, hindering the development of high-capacity storage solutions with increased reading/writing speeds, necessitating the transition to three-dimensional NAND flash memory.
Innovation Solution
A three-dimensional memory structure is formed with a stacked comb structure on a substrate, featuring doped regions, charge storage layers, and auxiliary gates to enhance uniformity, reliability, and turn-on current, achieved through ion implantation and specific patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar NAND flash memory is used, then manufacturing is simpler, but storage capacity is limited due to device critical dimension constraints
Solution Approach 1:
The patent transitions from planar two-dimensional memory architecture to three-dimensional stacked memory architecture. Multiple memory layers are stacked vertically with alternating semiconductor and insulating layers, enabling increased storage capacity by utilizing the vertical dimension while maintaining manufacturability through systematic layer stacking and patterning processes
2Quantity of substance
If device critical dimension is reduced for miniaturization, then storage density increases, but manufacturing precision requirements become excessively high
Solution Approach 1:
By stacking multiple memory layers vertically, the patent achieves high storage density without requiring extreme miniaturization of individual cell dimensions. The vertical stacking allows each layer to maintain manufacturable critical dimensions while the overall density increases through the number of stacked layers
Solution Approach 2:
The memory structure is divided into multiple discrete layers (semiconductor layers and insulating layers) that can be fabricated and patterned separately at relaxed critical dimensions, then stacked together. This segmentation allows each layer to be manufactured with standard precision while achieving high overall density through the stacked configuration
3Speed
If turn-on resistance is reduced to increase turn-on current, then reading/writing speed improves, but device reliability may deteriorate
Solution Approach 1:
The patent introduces auxiliary gates specifically at the bit line pad edge regions where low resistance is needed, while maintaining the original structure in other areas. This localized modification reduces turn-on resistance and improves speed without compromising the overall device reliability through widespread structural changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the uniformity and reliability of the device, reduces turn-on resistance, and increases turn-on current by creating a low-resistance path and depletion regions, thereby addressing the limitations of planar NAND flash memory.
Implementation Method 1
An ion implantation process is performed to the stepped structure, so as to form a doped region in the semiconductor layer below each step surface of the stepped structure
Data Source
AI summary
A method of forming a three-dimensional memory is provided. A stacked structure is patterned to form a comb structure including a bit line pad extending along a first direction and comb-teeth portions extending along a second direction. A charge storage layer is formed on top and sidewall of the comb structure. Bit lines and auxiliary gates are formed on the charge storage layer and extend along the first direction. Each bit line covers top and sidewall of partial comb-teeth portions. Auxiliary gates cover top and sidewall of edge regions of the bit line pad. The charge storage layer on top of the bit line pad is removed. The stacked structure of the bit line pad is patterned to form a stepped structure. An ion implantation is performed to the stepped structure, to form a doped region in the semiconductor layer below each step surface of the stepped structure.