3D NAND Memory Integration via Common Bit Line Architecture
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Solution Overview
Problem
Conventional three-dimensional stack structures in non-volatile memory devices face challenges in integrating memory cells and selecting layers due to increased word lines, which restricts integration level and complicates electrical reliability.
Innovation Solution
A non-volatile memory device with a three-dimensional stack structure that includes a plurality of NAND strings, a common bit line, a common source line, and string selection lines, where each NAND string has memory cells and transistors arranged in a NAND-cell array, with word lines common to selected memory cells and connected perpendicularly, allowing for enhanced integration and reliability through strategic transistor configurations and voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional NAND cell array is used to form a three-dimensional stack structure with increased layers, then the storage capacity is improved, but the number of word lines increases remarkably, leading to increased device complexity and restricted integration level
Solution Approach 1:
The patent merges multiple word line functions into a reduced set of word lines by implementing a three-dimensional stack structure where a single word line can select memory cells across multiple layers simultaneously. This consolidation reduces the total number of word lines required while maintaining the ability to address individual memory cells in the stacked configuration.
Solution Approach 2:
The patent transitions from a planar two-dimensional array to a three-dimensional stack structure, adding the vertical dimension for layer stacking. This dimensional change allows memory cells from different layers to be accessed through common word lines, reducing the number of word lines needed compared to a conventional two-dimensional expansion approach.
2Productivity
If the conventional NAND cell array is disposed perpendicular to the semiconductor substrate to increase integration, then the integration level is improved, but obtaining electrical reliability of channel layers becomes more difficult
Solution Approach 1:
The patent applies local quality by implementing different transistor types (enhancement-mode and depletion-mode) at specific locations within the NAND string. Depletion-mode transistors are used for string selection to provide always-on conduction for reliable signal application, while enhancement-mode transistors are used elsewhere. This localized differentiation ensures electrical reliability in the perpendicular stack configuration.
Solution Approach 2:
The patent introduces depletion-mode transistors as intermediary elements between the signal source and the memory cells in the stacked structure. These transistors act as reliable intermediaries that ensure consistent electrical connection and signal transmission through the vertical channel layers, overcoming the reliability challenges of perpendicular disposal.
3Quantity of substance
If more semiconductor layers are stacked to increase capacity, then the storage capacity is improved, but the number of circuits driving word lines increases, restricting integration level
Solution Approach 1:
The patent implements universality by designing word lines that can simultaneously select memory cells across multiple stacked layers. A single word line performs the multi-function of selecting cells in different layers, eliminating the need for separate word lines for each layer and reducing the number of driving circuits required.
Solution Approach 2:
The patent merges the word line selection function across multiple layers into a unified set of word lines. Instead of having separate word lines for each layer, the same word line structure is used to address memory cells in all stacked layers, consolidating the driving circuit requirements while maintaining high storage capacity.
Data Source
AI summary
A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.