3D NAND Flash Memory Common Source Plane Architecture
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Solution Overview
Problem
The existing vertical NAND string structures in memory devices are limited by impedance, restricting the number of stackable layers and hindering the achievement of higher memory capacity with increasing manufacturing costs.
Innovation Solution
A 3D memory device architecture featuring bottom and top memory cubes with a common source plane and vertical NAND string structures, allowing for multiple stackable layers and efficient programming and erasing of memory cells using dielectric charge trapping structures and independently addressable word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical NAND string structures are used to increase memory capacity, then storage density is improved, but the number of stackable layers is limited by impedance
Solution Approach 1:
The memory device is divided into multiple independent NAND strings, each with its own source connection. This segmentation allows each string to be independently controlled, reducing the cumulative impedance effect and enabling more layers to be stacked without exceeding impedance limits.
Solution Approach 2:
The patent transitions from a single-plane vertical structure to a multi-plane 3D architecture with bottom and top memory cubes separated by a common source plane. This dimensional change allows memory cells to be arranged in multiple stacked layers (increasing storage density) while maintaining manageable impedance through the distributed source connections across different planes.
2Quantity of substance
If more layers are stacked to increase memory capacity, then storage density is improved, but manufacturing cost increases
Solution Approach 1:
The common source plane serves multiple functions: it acts as the source for both bottom and top memory cubes, provides a reference potential for impedance control, and enables shared read/write operations across multiple layers. This multi-functionality reduces the need for additional separate source structures, thereby lowering manufacturing complexity and cost while supporting increased storage density.
3Device complexity
If impedance of vertical string is reduced to increase stackable layers, then number of layers is improved, but signal integrity may deteriorate
Solution Approach 1:
The common source plane acts as an intermediary between the bottom and top memory cubes, providing a stable reference potential that mediates signal transmission across the vertical distance. This intermediary structure helps maintain signal integrity by reducing voltage drops and impedance variations that would otherwise occur in longer vertical strings, enabling more layers to be stacked reliably.
Data Source
AI summary
A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.