3D NAND Contact Structure Reducing Chip Area and Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor memory devices with a three-dimensional structure face challenges in reducing chip area due to the complex extraction contact structure of electrode layers, which hampers the reduction of chip size and increases propagation delay.
Innovation Solution
The semiconductor memory device employs a novel contact structure where contact parts are formed in a protruding shape on the end parts of electrode layers, allowing direct electrical connection to circuit interconnections without traversing upper-layer interconnections, reducing the interconnection path length and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a plug is connected to each electrode layer processed into a staircase structure with upper-layer interconnections, then electrical connection between electrode layers and circuit interconnections is achieved, but chip area increases and propagation delay increases
Solution Approach 1:
The invention extracts and eliminates the unnecessary upper-layer interconnections from the extraction contact structure. By directly connecting plugs to electrode layers that protrude through the stacked body, the patent removes the intermediate routing layer, thereby reducing chip area while maintaining electrical connection reliability.
Solution Approach 2:
The patent utilizes the vertical dimension by having electrode layers protrude through the stacked body in the stacking direction. This allows plugs to connect directly from the protruding end parts to circuit interconnections on the substrate, bypassing the need for horizontal routing through upper-layer interconnections, thus reducing chip area.
2Reliability
If a plug is connected to each electrode layer processed into a staircase structure with upper-layer interconnections, then electrical connection between electrode layers and circuit interconnections is achieved, but propagation delay increases
Solution Approach 1:
The invention extracts and eliminates the unnecessary upper-layer interconnections from the extraction contact structure. By directly connecting plugs to electrode layers that protrude through the stacked body, the patent removes the intermediate routing layer, thereby reducing chip area while maintaining electrical connection reliability.
Solution Approach 2:
The patent implements a direct connection path where plugs extend from protruding electrode layers directly to circuit interconnections on the substrate, skipping the intermediate upper-layer interconnection routing step. This shortens the signal transmission path and reduces propagation delay.
3Reliability
If electrode layers are processed into a staircase structure with complex extraction contact, then electrical connection is achieved, but device complexity increases
Solution Approach 1:
The invention extracts and eliminates the unnecessary upper-layer interconnections from the extraction contact structure. By directly connecting plugs to electrode layers that protrude through the stacked body, the patent removes the intermediate routing layer, thereby reducing chip area while maintaining electrical connection reliability.
Data Source
AI summary
According to one embodiment, the stacked body includes a plurality of electrode layers and a plurality of insulating layers alternately stacked on the substrate. The plurality of contact parts are provided in a protruding shape on respective end parts of the plurality of electrode layers. The plurality of contact parts do not overlap each other in the stacking direction. The plurality of contact parts are displaced in a surface direction of the substrate. The plurality of plugs extends from the respective contact parts toward the respective circuit interconnections and electrically connects the respective contact parts with the respective circuit interconnections.