3D NAND Through-Array Contacts for Easier Vertical Interconnect Etching
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and increasing costs, necessitating a transition to three-dimensional (3D) memory architectures to enhance memory density.
Innovation Solution
The development of three-dimensional (3D) NAND memory devices with through array contact (TAC) structures, featuring an alternating layer stack with dielectric and conductor/dielectric layer pairs, barrier structures, and through array contacts to facilitate vertical interconnects between memory arrays and peripheral circuits, reducing process complexity and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling is pursued, then memory density is improved, but feature size approaches lower limit and manufacturing cost increases
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by stacking alternating dielectric and conductor/dielectric layers vertically. This dimensional change allows memory density to increase without further reducing lateral feature sizes, thereby avoiding the manufacturing precision challenges and cost increases associated with sub-lower-limit feature scaling.
2Quantity of substance
If 3D memory architecture is implemented, then memory density is improved, but device complexity increases
Solution Approach 1:
The 3D memory architecture is segmented into alternating dielectric layers and conductor/dielectric layers, each serving distinct functions. The alternating dielectric layers provide insulation and structural support, while the conductor/dielectric layers contain conductive pathways for data storage and retrieval. This segmentation simplifies the overall device complexity by dividing the 3D structure into manageable, functionally distinct repeating units.
Solution Approach 2:
The alternating layer stack structure serves multiple functions simultaneously: it provides vertical stacking for high density, electrical insulation through dielectric layers, conductive pathways through conductor layers, and mechanical support. This multi-functionality reduces device complexity by consolidating multiple requirements into a single integrated structure rather than requiring separate components for each function.
3Quantity of substance
If alternating conductor/dielectric stack is used, then memory density is improved, but manufacturing difficulty increases due to etching complexity
Solution Approach 1:
The patent creates local quality differentiation by forming through-array contacts (TACs) that selectively extend through alternating dielectric layers while terminating before penetrating conductor layers. This local modification allows the etching process to be simpler (stopping at dielectric/conductor interfaces) rather than requiring complex through-etching of the entire alternating stack, thereby improving ease of manufacture while maintaining the high-density 3D architecture.
Data Source
AI summary
Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure including two parallel barrier walls extending vertically through the alternating layer stack and laterally along a word line direction to laterally separate the first region from the second region. The memory device further comprises a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack.