3D NAND Contact Structure Layout for Lower ACS Resistance
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Solution Overview
Problem
3D NAND memory devices face challenges with decreasing channel saturation current and increasing ACS resistance as the number of layers increases, affecting reliability and performance.
Innovation Solution
The semiconductor device incorporates a semiconductor layer between two stacks with contact and channel structures extending through both, connecting top and bottom bit lines, reducing channel length and ACS resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers is increased to increase memory density, then the array density is improved, but the channel saturation current decreases and ACS resistance increases
Solution Approach 1:
The bit line connection path is segmented into multiple sections by introducing intermediate ACS layers at different heights. Instead of a single long vertical path, the connection is divided into shorter segments that are horizontally bridged by intermediate ACS layers, reducing the effective channel length and improving current saturation characteristics
Solution Approach 2:
The patent introduces horizontal connection paths between vertical stacks by adding intermediate ACS layers at different heights. This transforms the purely vertical current path into a three-dimensional path that alternates between vertical and horizontal segments, effectively shortening the vertical channel length while maintaining the layered structure
2Quantity of substance
If the number of layers is increased to increase memory density, then the array density is improved, but the ACS resistance increases
Solution Approach 1:
The long vertical ACS path is segmented into multiple shorter vertical sections separated by horizontal intermediate ACS layers. Each segment has lower resistance, and the parallel horizontal connections provide additional current paths, reducing the total ACS resistance
Solution Approach 2:
Intermediate ACS layers are introduced at different heights to create horizontal connection paths between vertical stacks. This adds a horizontal dimension to the current path, creating parallel conduction paths that reduce the overall ACS resistance while maintaining the vertical stacking for high density
Data Source
AI summary
The present disclosure relates to methods, devices, systems, and techniques for managing contact structures in semiconductor devices. An example semiconductor device includes a first semiconductor structure. The first semiconductor structure includes: a first stack of conductive layers and isolating layers alternating with each other along a first direction; a second stack of conductive layers and isolating layers alternating with each other along the first direction; a semiconductor layer between the first stack and the second stack along the first direction; a contact structure connected to the semiconductor layer, where the contact structure extends through the first stack, the semiconductor layer, and the second stack along the first direction; and a channel structure extending through the first stack, the semiconductor layer, and the second stack along the first direction, where the semiconductor layer is in contact with a channel layer of the channel structure.