3D NAND Contact Structure for Dense Vertical Memory Integration
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Solution Overview
Problem
There is a need for semiconductor devices with increased data storage capacity and improved integration density and productivity.
Innovation Solution
The semiconductor device includes a first structure with a substrate, circuit devices, and pad layers, and a second structure with a pattern structure having openings and gate electrodes stacked vertically, channel structures penetrating through the stack, and contact plugs connecting to the pad layers, enhancing integration density and productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but device complexity increases
Solution Approach 1:
The patent implements vertically stacked memory cells arranged in three dimensions rather than traditional two-dimensional planar arrangements. Multiple memory cell layers are stacked above each other, with gate electrodes extending in the vertical direction, thereby increasing storage capacity by utilizing the third dimension (height) of the device structure.
Solution Approach 2:
The memory device is divided into multiple distinct functional layers including first and second pad layers, pattern structures with openings, stacked gate electrodes, channel structures, contact plugs, and insulating layers. Each layer performs a specific function and can be independently fabricated and optimized, which manages the overall device complexity through modular segmentation.
2Quantity of substance
If vertically stacked gate electrodes and channel structures are implemented, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves high integration density by stacking gate electrodes and channel structures in the vertical direction. Multiple gate electrodes are arranged one above another with insulating layers in between, creating a three-dimensional integrated structure that packs more functional elements into a smaller planar footprint.
Solution Approach 2:
The fabrication process employs preliminary patterning actions where pad layers and pattern structures are formed first with precise openings, followed by sequential deposition and patterning of gate electrodes and channel structures. This step-by-step preliminary preparation ensures that each subsequent layer can be accurately positioned, maintaining manufacturing precision throughout the complex stacking process.
3Reliability
If multiple pad layers and complex connection structures are used, then electrical connection reliability is improved, but ease of manufacture decreases
Solution Approach 1:
The electrical connection structure is segmented into multiple functional components: first pad layers for initial connections, second pad layers for upper-level connections, pattern structures with openings that guide alignment, contact plugs that penetrate through insulating layers, and source connection patterns. Each segment can be independently fabricated and tested, improving overall connection reliability while allowing modular manufacturing.
Solution Approach 2:
The patent introduces intermediary structures such as insulating layers with openings and pattern structures that act as mediators between different connection layers. These intermediary elements facilitate precise alignment and electrical connection between pad layers, contact plugs, and gate electrodes, ensuring reliable connections while maintaining ease of manufacture through standardized intermediary components.
Data Source
AI summary
A semiconductor memory device including a substrate, first pad layers and a second pad layer on the substrate, a pattern structure including first openings on the first pad layers and a second opening on the second pad layer, and having first and second regions, gate electrodes on the pattern structure and each including a pad region, channel structures penetrating through the gate electrodes in the first region, gate contact plugs electrically connected to the gate electrodes through the pad region of each of the gate electrodes and extending in a vertical direction to penetrate the first openings and connected to the first pad layers, a source contact plug, extending in the vertical direction penetrating the second opening and connected to the second pad layer, and a source connection patter under the pattern structure and in contact with the source contact plug and the second pad layer may be provided.