3D NAND Contact Structure With Spacer-Formed Flat Peripheral Contacts
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Solution Overview
Problem
The fabrication of peripheral contacts in 3D NAND memory devices is complex and lengthy due to the two-step etch and deposition processes, which complicates the formation of second contact portions and leads to undesirable protrusions on the contact surfaces.
Innovation Solution
The fabrication process is simplified by forming a spacer structure on the front side of the base structure using an etch process followed by deposition, which integrates seamlessly into the existing process flow without additional steps, and the second contact portion is formed within the spacer structure to reduce etching complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then existing manufacturing capabilities are maintained, but feature size scaling to 10 nanometer node and below cannot be achieved
Solution Approach 1:
The pitch refinement process is segmented into multiple distinct stages: initial pitch formation, first pitch collapse phase, intermediate pitch reformation, second pitch collapse phase, and final mandrel removal. Each stage is independently optimized to achieve cumulative precision improvements that enable 10nm node scaling while maintaining process control and reliability.
Solution Approach 2:
Mandrels are formed in advance with precise dimensions and positions before the pitch refinement process begins. These pre-formed mandrels serve as templates that guide subsequent material deposition and self-aligned patterning, ensuring feature placement accuracy is established early in the process before variability can accumulate.
2Productivity
If feature sizes are reduced to enable higher transistor density, then device capacity increases, but fabrication process control becomes more difficult
Solution Approach 1:
The pitch refinement structure employs nested patterning where smaller features are formed within and around larger mandrel structures. Multiple pitch layers are nested relative to each other, with each layer serving as a reference for the next, enabling progressive feature size reduction while maintaining alignment precision through self-aligned processes.
Solution Approach 2:
Traditional mechanical lithography alignment methods are replaced with self-aligned chemical and physical processes. The pitch refinement utilizes self-aligned deposition and etching where previously formed structures automatically define the positions of subsequent features, eliminating mechanical alignment errors and enabling precise sub-10nm feature fabrication.
3Length of moving object
If pitch refinement is performed to achieve smaller features, then device miniaturization is enabled, but the fabrication process becomes more complex
Solution Approach 1:
The pitch refinement process employs periodic cycles of material deposition, collapse, reformation, and removal repeated multiple times. Each cycle refines the pitch by a specific factor, and by repeating the cycle with adjusted parameters, the desired final pitch is achieved. This periodic approach breaks down the complex miniaturization task into manageable, repeatable stages.
Solution Approach 2:
Mandrels serve as intermediary structures that facilitate pitch refinement without being part of the final device. These temporary structures enable precise feature formation through self-aligned processes, then are removed after serving their patterning function. The mandrels mediate between the fabrication equipment capabilities and the desired final feature dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process by reducing the need for lengthy etching and deposition steps, resulting in a more efficient and reliable formation of peripheral contacts with a flat upper surface, enhancing the overall manufacturing efficiency of 3D NAND memory devices.
Implementation Method 1
a first pitch structure using a sacrificial material
Implementation Method 2
collapsing the first pitch structure to a first collapsed pitch structure
Implementation Method 3
removing the first collapsed pitch structure
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
Methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device (200) includes an insulating layer (202), a conductive layer (208) over the insulating layer (202), and a spacer structure (220) in the conductive layer (208) and in contact with the insulating layer (202). The semiconductor device (200) also includes a first contact structure (216) in the spacer structure (220) and extending vertically through the insulating layer (202). The first contact structure (216) includes a first contact portion (216-1) and a second contact portion (216-2) in contact with each other. An upper surface of the second contact portion (216-2) is coplanar with an upper surface of the conductive layer (208).