3D NAND Control Gate Enhancement via Conformal Blocking Liner
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Solution Overview
Problem
Current 3D NAND memory devices face challenges in reducing cell-to-cell interference while maintaining a high coupling ratio between the control gate and floating gate, especially at vertical pitches of 20 nm or less, which affects device performance and chip density.
Innovation Solution
The solution involves forming a NAND memory structure with a conformal blocking oxide liner and a silicon channel, where the floating gate is electrically isolated from the control gate, and a metal gate material is used to fill gaps between oxide layers, reducing vertical pitch and enhancing charge retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the vertical pitch between layers is decreased to increase chip density, then the number of structures per unit area increases, but cross-talk between neighboring cells increases and device performance deteriorates
Solution Approach 1:
A conformal blocking oxide liner is introduced as an intermediary layer between adjacent memory cells. This oxide liner acts as a mediator that electrically isolates neighboring cells, preventing cross-talk while allowing the vertical pitch to remain small for high density. The blocking oxide is deposited conformally on the sidewalls of the charge trap layer, creating effective electrical barriers between adjacent cells.
Solution Approach 2:
The blocking oxide liner is segmented into discrete portions located at specific positions around the charge trap layer. Rather than a continuous structure, the blocking oxide is formed in segments that provide electrical isolation where needed while maintaining compatibility with the overall cell structure and allowing charge storage functionality.
2Object-affected harmful factors
If the surface area of charge-trap layers is increased to reduce cross-talk, then cell-to-cell interference decreases, but the vertical pitch between layers would increase
Solution Approach 1:
Instead of increasing the surface area of the charge-trap layer in the lateral dimension, the blocking oxide liner extends into the vertical dimension by conformally coating the sidewalls of the charge trap layer. This vertical extension provides additional isolation path length without increasing the lateral footprint or vertical pitch between memory layers, effectively reducing cell-to-cell interference while maintaining compact vertical stacking.
3Productivity
If 3D NAND devices are scaled down to vertical pitch of 20 nm or less, then chip density increases, but cell functionality deteriorates due to increased cell-to-cell interference
Solution Approach 1:
The blocking oxide liner is positioned locally at critical interfaces where cell-to-cell interference occurs, specifically on the sidewalls of the charge trap layer adjacent to neighboring cells. This localized placement provides targeted electrical isolation exactly where needed to protect cell functionality, while not interfering with the overall scaling to 20 nm or less vertical pitch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces cell-to-cell interference and maintains high cell functionality, enabling higher charge retention and improved performance in dense 3D NAND memory devices.
Implementation Method 1
a conformal blocking oxide liner along the first side, the second side, and the third side of the floating gate material and along a face of the first and second insulating layers facing the memory hole channel, such that the conformal blocking oxide liner electrically isolates the control gate material from the floating gate material
Implementation Method 2
a gate oxide material contacting the fourth side of the floating gate material and the conformal blocking oxide liner adjacent the face of the first and second insulating layers
Data Source
AI summary
Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.