3D NAND Memory Integration with Control Logic

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Solution Overview

Problem

Microelectronic device designers face challenges in increasing memory density and performance while reducing the size and fabrication costs of memory devices, particularly due to limitations in processing conditions and configurations of control logic devices within the base control logic structure of non-volatile memory devices like 3D NAND Flash memory.

Innovation Solution

The method involves forming a microelectronic device structure with a base structure, a doped semiconductive material, a stack structure with alternating conductive and insulative layers, semiconductive structures extending through the base, and cell pillar structures, which are integrated with control logic devices to enhance memory cell density and performance, allowing for more compact and efficient design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If control logic devices are formed using conventional processing conditions over the base control logic structure, then the memory array can be formed with vertical stacking architecture, but the control logic devices are limited in configuration and performance

Engineering Contradiction:

Improvecontrol logic device performanceVSAvoidcontrol logic device configuration flexibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The device is segmented into two separately formed structures: a memory array structure formed first with its own processing conditions, and a control logic structure formed second with different processing conditions. This segmentation allows each structure to be optimized independently, resolving the contradiction between performance reliability and configuration flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory array structure is formed in advance before the control logic structure. This preliminary action allows the memory array to be established with optimal processing conditions first, then the control logic can be added subsequently with different processing conditions, enabling both high performance and configuration flexibility.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If the quantities, dimensions, and arrangements of control logic devices are increased to improve functionality, then more features can be integrated, but the horizontal footprint of the memory device increases

Engineering Contradiction:

Improvecontrol logic functionalityVSAvoidhorizontal footprint

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The control logic structure is formed in a separate dimensional space above the memory array structure, rather than expanding horizontally. This vertical integration in another dimension allows increased functionality without increasing the horizontal footprint of the device.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The control logic structure is nested above the memory array structure, with the control logic forming an overlying layer. This nesting arrangement allows both structures to coexist in a compact configuration, providing enhanced functionality while maintaining a small horizontal footprint.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Ease of manufacture

If conventional processing conditions are used for forming the memory array over the base control logic structure, then fabrication can proceed with standard processes, but the control logic devices cannot achieve optimal performance

Engineering Contradiction:

Improvefabrication process standardizationVSAvoidcontrol logic device performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The fabrication process is segmented into two independent sequences: first forming the memory array structure with standard processing conditions, then forming the control logic structure with optimized processing conditions. This segmentation allows each structure to receive appropriate processing treatment without compromising ease of manufacture or device performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different processing parameters are applied to different structures: standard processing parameters for the memory array structure and optimized processing parameters for the control logic structure. This parameter differentiation enables optimal performance for each structure while maintaining overall ease of manufacture through systematic process control.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11335602B2Methods of forming microelectronic devices, and related microelectronic devices and electronic systems

Publication Date: 2022.05.17 MICRON TECHNOLOGY INC

AI summary

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure; a doped semiconductive material overlying the base structure; a stack structure overlying the doped semiconductive material; semiconductive structures extending from within the base structure, through the doped semiconductive structure, and into a lower portion of the stack structure; cell pillar structures horizontally aligned with the semiconductive structures and vertically extending through an upper portion of the stack structure; and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form an assembly. The base structure and portions of the semiconductive structures are removed. The doped semiconductive material is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.