3D NAND and CPU Hybrid Bonding for Dense Chip Stacking
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Solution Overview
Problem
Traditional two-dimensional (2D) planar integrated circuits face limitations in density and performance as feature sizes approach fundamental limits, making three-dimensional (3D) ICs necessary for higher density and bandwidth, but existing 3D IC technologies like Through-Silicon-Via (TSV) are limited by large lateral dimensions and pitch, restricting the number of interconnects and performance improvement.
Innovation Solution
The method involves forming a 3D semiconductor device by creating vertical interconnect structures through substrates and using hybrid bonding technology to integrate dynamic random-access memory (DRAM), NAND flash memory, or other functional chips with a central processing unit (CPU) chip, enabling thousands or millions of metal interconnects for a super chip, such as a computer-on-a-chip, with dielectric-to-dielectric and metal-to-metal bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If Through-Silicon-Via (TSV) technology is used for 3D IC integration, then vertical interconnect is achieved, but lateral dimensions and pitch are large, restricting the number of interconnects
Solution Approach 1:
The patent transitions from planar 2D interconnect architecture to three-dimensional stacked architecture, enabling vertical interconnect pathways that bypass the lateral dimension limitations of TSV technology. Multiple memory chips are stacked vertically with interconnect structures extending through substrates, achieving high interconnect density without being constrained by lateral pitch requirements.
Solution Approach 2:
The patent implements nested interconnect structures where conductive pathways are embedded within dielectric layers that are themselves embedded within chip substrates. The interconnect structures include conductive lines, contact holes, and via holes nested within multiple dielectric layers, creating a hierarchical nested architecture that maximizes interconnect density.
2Quantity of substance
If planar IC scaling continues, then feature sizes reduce, but density and bandwidth approach upper limits
Solution Approach 1:
The patent resolves the density bottleneck by stacking multiple functional chips vertically to form a three-dimensional integrated circuit architecture. This vertical stacking enables continuous scaling of device density without further reducing lateral feature sizes, thereby avoiding the fabrication complexity and physical limits associated with aggressive planar scaling.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate functional chips (e.g., CPU chip, memory chips) that are fabricated independently and then stacked vertically. This segmentation allows each chip to be optimized separately while achieving high overall system density through vertical integration, bypassing the need for continuous planar scaling.
3Power
If multiple memory chips are stacked with a CPU chip, then bandwidth and density improve, but substrate thickness increases
Solution Approach 1:
The patent implements nested interconnect structures where conductive pathways are embedded within dielectric layers that are themselves embedded within chip substrates. The interconnect structures include conductive lines, contact holes, and via holes nested within multiple dielectric layers, creating a hierarchical nested architecture that maximizes interconnect density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in 3D ICs with smaller size, higher density, higher bandwidth, and improved performance (speed and power efficiency) compared to traditional 3D ICs, facilitating the integration of multiple memory and logic chips into a single, high-performance device.
Implementation Method 1
hybrid bonding technology to integrate dynamic random-access memory (DRAM), NAND flash memory, or other functional chips with a central processing unit (CPU) chip, enabling thousands or millions of metal interconnects for a super chip
Implementation Method 2
the thinning comprises grinding, wet or dry etching, or chemical-mechanical polishing
Implementation Method 3
the thinning comprises grinding, wet or dry etching, or chemical-mechanical polishing
Data Source
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AI summary
Embodiments of three-dimensional semiconductor devices and fabrication methods are disclosed. The method includes forming a first and a second memory chips and a microprocessor chip. The method also includes bonding a first interconnect layer of the first memory chip with a second interconnect layer of the second memory chip, such that one or more first memory cells of the first memory chip are electrically connected with one or more second memory cells of the second memory chip through interconnect structures of the first and second interconnect layers. The method further includes bonding a third interconnect layer of the microprocessor chip with a substrate of the second memory chip, such that the one or more microprocessor devices of the microprocessor chip are electrically connected with one or more second memory cell of the second memory chip through interconnect structures of the second and third interconnect layers.