3D NAND Data Mapping for Lifetime Capacity
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Solution Overview
Problem
NAND flash memory devices can only be written once, leading to limited lifetime and storage capacity, as erasure by blocks is time and energy consuming, and degrades physical cells.
Innovation Solution
Implementing data mapping based on three-dimensional lattices that allow writing data multiple times prior to erasure, using rewriting codes that enable low read latency and increased storage capacity by optimizing bit allocation and read thresholds, thereby improving the sum-rate (lifetime capacity) of NAND flash memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written to a memory location only once before erasure, then the write operation is simple and fast, but the storage capacity and lifetime of the NAND device are limited
Solution Approach 1:
The patent applies preliminary action by writing data to a memory location multiple times before performing erasure. Specifically, the system writes a first set of data, then writes a second set of data to the same location before erasing. This preliminary rewriting action increases the effective storage capacity and extends device lifetime without requiring complex additional hardware, as the controller simply manages multiple write operations to the same physical location before erasure.
2Productivity
If block erasure is performed to reuse memory locations, then the memory can be reused, but the process is time and energy consuming and degrades physical cells
Solution Approach 1:
The system performs preliminary write operations multiple times before erasure, maximizing the utilization of each memory location before it needs to be erased. By writing both a first set of data and a second set of data to the same location before erasure, the system extracts maximum value from each write operation, reducing the frequency of erasure operations and thereby reducing time and energy loss.
Solution Approach 2:
The patent applies discarding and recovering by selectively overwriting data in memory locations before erasure. The controller identifies which memory locations can be rewritten with new data before erasure and performs those writes to maximize data density. This selective approach recovers additional storage capacity from existing locations without requiring immediate erasure of entire blocks, thus reducing the frequency and impact of erasure operations.
3Quantity of substance
If multiple writes are performed to the same memory location before erasure, then storage capacity increases, but the read latency may increase
Solution Approach 1:
The patent applies local quality by implementing different write strategies for different memory locations based on their access patterns and characteristics. The controller identifies which locations benefit most from multiple writes and applies the multi-write strategy selectively to those locations, while maintaining standard single-write procedures for locations where it would not provide benefit. This localized approach maximizes capacity improvements without unnecessarily increasing read latency across the entire memory array.
Data Source
AI summary
In this disclosure, data mapping based on three dimensional lattices that have an improved sum rate (i.e., lifetime capacity) with low read latency is disclosed. During the write, a memory location is written to multiple times prior to erasure. Specifically, for the first write, there are 4/3 bits per cell available for writing, which is about 10.67 kB per cell are used for data storage. Then, for the second write, there is one bit per cell, which is 8 kB per cell for data storage. If considering a block with 128 different cells and writing 32 kB of data, the first write results in 42.66 data writes while the second write results in 32 writes for a total of 74.66 writes. Previously, the number of writes for 32 kB would be 64 writes. Thus, by writing twice prior to erasure, more data can be stored.