3D NAND Deck-by-Deck Erase Verify and Dynamic Inhibit
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Solution Overview
Problem
In multi-deck memory architectures, accurately determining the erase state of memory cells is challenging due to increased series string resistance from external factors, leading to erroneous determinations and unnecessary erase operations, especially in long series strings.
Innovation Solution
Implementing a deck-by-deck erase verify scheme where memory cells in one deck are activated with a high cell activation voltage while cells in another deck are verified with an erase verify voltage, reducing series string resistance and improving accuracy by independently verifying each deck.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional erase verify is used in multi-deck memory architectures, then the process is simpler, but measurement precision deteriorates due to increased series string resistance leading to erroneous erase state determinations
Solution Approach 1:
The verify operation is segmented into deck-specific operations where each deck is verified independently. The controller applies deck-specific verify voltages to wordlines in different decks, allowing separate measurement of erase states without interference from other decks. This segmentation eliminates the series string resistance problem that affected traditional multi-deck verify operations.
Solution Approach 2:
Different verify voltages are applied to different decks based on their specific characteristics. The controller determines deck-specific verify voltages and applies them selectively to each deck's wordlines. This local quality approach allows each deck to be verified with optimal voltage levels, improving measurement precision while accounting for variations in erase performance between decks.
2Reliability
If traditional erase operations are performed on all decks, then throughput is maintained, but loss of substance increases due to unnecessary erase operations and over-erasing of already erased cells
Solution Approach 1:
The controller performs preliminary verify operations on each deck before executing the full erase sequence. By verifying the erase state of each deck individually using deck-specific voltages, the controller can identify which decks are already properly erased and should not undergo additional erase operations. This preliminary action prevents unnecessary erasure and protects cells from over-erasing while maintaining efficient throughput by only erasing decks that need it.
3Measurement precision
If deck-by-deck erase verify is implemented, then measurement precision improves, but use of energy increases due to multiple voltage levels and extended verify operations
Solution Approach 1:
The controller dynamically adjusts verify voltage parameters based on deck-specific characteristics and erase progress. By determining optimal deck-specific verify voltages and applying them selectively, the system achieves high measurement precision without unnecessarily applying high voltages to all decks throughout the entire verify process. This parameter optimization reduces energy consumption while maintaining accurate erase state detection.
Data Source
AI summary
In one embodiment, an apparatus comprises a controller to determine an erase state of a first memory deck independently from an erase state of a second memory deck, the first memory deck comprising a first plurality of wordlines and a first channel, the first memory deck comprising a first plurality of memory cells that are each coupled to the first channel and a respective one of the first plurality of wordlines; the second memory deck comprising a second plurality of wordlines and a second channel, the second channel coupled to the first channel, the second memory deck comprising a second plurality of memory cells that are each coupled to the second channel and a respective one of the second plurality of wordlines; and determine an erase state of the second memory deck independently from an erase state of the first memory deck.