3D NAND Deck-Specific Read Level Management
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Solution Overview
Problem
Memory devices with 3D NAND architecture experience performance degradation and errors due to charge imbalances across different decks caused by programming delays, leading to inconsistent read voltage levels.
Innovation Solution
Implementing a time-based read level management mechanism that dynamically adjusts read levels by measuring the deck separation delay and using a lookup table or equations to calculate offset values, allowing for deck-specific read levels to maintain data integrity and reduce error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory devices use fixed read voltage levels for all decks, then device complexity is reduced, but data integrity deteriorates due to charge loss variations over time
Solution Approach 1:
The patent implements dynamic read level adjustment by tracking programming times of different decks and calculating time-based offsets. The read level for each deck is dynamically modified based on the time elapsed since its last programming operation, allowing the system to adapt to charge loss variations without requiring complex hardware modifications.
Solution Approach 2:
The patent changes the read voltage parameter based on time elapsed since programming. By calculating offset values based on programming time differences between decks and applying these as voltage offsets, the system adjusts the read level parameter to compensate for charge loss, thereby maintaining data integrity across decks with different programming times.
2Manufacturing precision
If memory devices apply uniform read levels to all decks, then manufacturing precision requirements are reduced, but error rates increase due to charge imbalances
Solution Approach 1:
The patent applies different read levels to different decks based on their individual programming times. Each deck receives a customized read level offset calculated from its specific programming time relative to other decks, ensuring that each deck is read with the optimal voltage level for its charge state rather than using a uniform read level for all decks.
3Reliability
If memory devices implement time-based read level adjustment, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary tracking of programming times for each deck and pre-calculates the time offsets before read operations. By maintaining a record of when each deck was programmed and pre-determining the appropriate read level offsets, the system prepares the necessary compensation data in advance, reducing the complexity of real-time read level management during actual read operations.
4Ease of operation
If memory devices use single read level for all decks, then ease of operation is improved, but measurement precision of charge levels deteriorates
Solution Approach 1:
The patent modifies the read voltage parameter based on the time elapsed since each deck was programmed. By calculating time-based offsets and applying them to the base read level, the system adjusts the measurement conditions to account for charge loss, thereby improving charge level detection accuracy while maintaining relatively simple operation through automated offset application.
Data Source
AI summary
Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.