3D NAND Flash Memory Decoder Stacking for Wiring Reduction
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Solution Overview
Problem
NAND flash memories with a three-dimensional structure face challenges in reducing the number of wirings perpendicular to memory cell layers as the number of stacked layers increases, leading to decreased chip area efficiency.
Innovation Solution
The implementation of a memory device with a decoder and memory cell portion structured in specific layers, utilizing a single crystal silicon substrate and metal oxide transistors to control and select memory cells, reducing the need for additional wirings by integrating the decoder above the memory cell layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cell layers is increased to increase storage capacity, then storage capacity is improved, but the number of wirings provided substantially perpendicular to memory cell layers is increased and chip area is increased
Solution Approach 1:
The patent applies dimensionality change by stacking the decoder layer above the memory cell layer in the vertical direction (third dimension). This allows the decoder to be positioned at a different spatial level rather than expanding horizontally, thereby reducing the footprint area and the number of perpendicular wirings needed to connect components while maintaining high storage capacity through increased memory cell layers.
Solution Approach 2:
The patent implements nesting by integrating the decoder structure within the vertical stack of the memory device. The decoder is nested above the memory cell layer, sharing the same vertical space and utilizing the stacked architecture. This nested configuration allows both the memory cells and decoder to coexist in a compact three-dimensional structure, reducing overall chip area and wiring complexity.
2Quantity of substance
If the number of memory cell layers is increased to increase storage capacity, then storage capacity is improved, but chip area efficiency is decreased
Solution Approach 1:
The patent utilizes vertical stacking in the third dimension to accommodate both memory cell layers and the decoder. By positioning the decoder above the memory cell layer rather than placing it side-by-side in the planar direction, the design maximizes the use of vertical space, thereby improving chip area efficiency while maintaining high storage capacity through increased numbers of memory cell layers.
Solution Approach 2:
The patent merges the decoder and memory cell portion into a single integrated three-dimensional structure. The decoder is combined with the memory cell array in a stacked configuration, allowing both functional blocks to share the same chip area efficiently. This merging eliminates the need for separate horizontal spaces for decoder and memory cells, thereby improving overall chip area efficiency.
3Productivity
If more wirings are provided perpendicular to memory cell layers to support increased layers, then data transmission capability is improved, but manufacturing complexity and cost are increased
Solution Approach 1:
The patent reduces manufacturing complexity by repositioning the decoder in the vertical dimension above the memory cell layer. This dimensional rearrangement decreases the number of perpendicular wirings required to connect the decoder to memory cells, as the decoder is now adjacent to the memory cell stack rather than being remotely connected through multiple wiring layers. This simplifies the wiring architecture and reduces manufacturing steps while maintaining data transmission capability.
Data Source
AI summary
A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.