3D NAND Vertical Transistor Strings With Differential Etch Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As 3D NAND memory devices transition to higher densities with more memory cell layers, the challenge of improving manufacturing structures and methods becomes increasingly complex, particularly in maintaining uniformity and reducing discontinuities in the via profiles.
Innovation Solution
The semiconductor device incorporates a string of transistors stacked vertically, with specific insulating layers having different etch rates to manage discontinuities. The method involves forming stacks with alternating insulating and gate layers, where the second insulating layers etch faster than the third, allowing for controlled via formation and reduction of discontinuities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used, then manufacturing process is simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from planar 2D transistors to three-dimensional vertically-stacked transistors, stacking multiple transistor layers vertically over a common substrate. This dimensional change increases device density by utilizing the vertical space above the substrate rather than only horizontal plane, allowing multiple active devices to occupy a smaller footprint area while maintaining manufacturability through sequential formation processes.
2Productivity
If multiple transistor substrings are stacked vertically, then device density increases, but selective removal and processing difficulty increases
Solution Approach 1:
The patent introduces sacrificial insulating layers with different etch rates at specific locations between transistor substrings. The first sacrificial insulating layer has a first etch rate while the second sacrificial insulating layer has a second etch rate that is faster than the first. This local differentiation in material properties enables selective removal of specific substrings through etching processes, allowing individual substrubing extraction or replacement without affecting adjacent substrings, thus maintaining manufacturing ease despite vertical stacking complexity.
Solution Approach 2:
The patent changes the etch rate parameter of sacrificial insulating layers by using different materials or compositions for different layers. The first sacrificial insulating layer and second sacrificial insulating layer are formed with distinct etch rates, which are controlled through material selection and deposition parameters. This parameter variation enables selective etching processes to remove specific substrings while preserving others, solving the selective removal challenge in vertically-stacked architectures.
3Ease of manufacture
If sacrificial insulating layers with different etch rates are used, then selective substrate removal is enabled, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the insulating layer structure into multiple segmented sacrificial insulating layers, where each layer serves a specific function in the selective removal process. The first sacrificial insulating layer is positioned between certain substrings while the second sacrificial insulating layer is positioned between other substrings, with each layer having tailored etch rate characteristics. This segmentation allows independent control and removal of different substrate groups through sequential etching steps, enabling complex device architectures to be built through modular, stepwise manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced discontinuities between critical dimensions in the via profiles, leading to a smoother edge and more uniform layer thicknesses in the channel structure, thereby enhancing the performance and efficiency of the semiconductor device.
Implementation Method 1
the second insulating layers have a higher etch rate than that of the third insulating layers
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. The semiconductor device includes a string of transistors stacked in a vertical direction over a substrate of the semiconductor device having a channel structure extending in the vertical direction. The string of transistors includes first, second, and third substrings of transistors that are arranged along first, second, and third portions of the channel structure, respectively. Gate structures of transistors in the first, second, and third substring are separated by respective first, second, and third insulating layers and the second insulating layers have a higher etch rate than that of the third insulating layers.