3D NAND Contact Structure With Diffusion Barrier Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and reliability, particularly in electronic systems requiring high-capacity data storage, where traditional two-dimensional memory cells are insufficient.
Innovation Solution
A semiconductor device design featuring a first and second substrate structure with gate electrodes stacked and spaced apart, channel structures penetrating through the gate electrodes, and diffusion barriers between contact plugs and the source structure, enhancing electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged two-dimensionally, then device structure is simple, but data storage capacity is limited
Solution Approach 1:
The patent implements three-dimensional memory cell arrangement where memory cells are stacked vertically across multiple substrate structures (first substrate structure, second substrate structure, third substrate structure) connected via through-substrate vias. This vertical stacking transitions from two-dimensional to three-dimensional spatial utilization, dramatically increasing data storage capacity while maintaining manageable structural complexity through modular design and standardized interconnection patterns.
2Reliability
If contact plugs directly contact source structure, then electrical connection is simple, but metal diffusion occurs reducing reliability
Solution Approach 1:
The patent introduces a diffusion barrier layer positioned between the contact plug and the source structure. This intermediary layer prevents metal atoms from diffusing into the source structure during device operation and fabrication processes, thereby maintaining electrical integrity and device reliability. The diffusion barrier serves as a protective mediator that blocks harmful atomic migration while allowing electrical current to pass through the contact plug to the source structure.
3Quantity of substance
If gate electrodes are stacked closely, then data storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the gate electrode structure into multiple discrete segments stacked vertically across different substrate structures. Each gate electrode layer is formed as a separate entity on its respective substrate, allowing independent fabrication and alignment. The through-substrate vias and bonding interfaces provide standardized registration features that facilitate precise alignment during assembly, reducing the overall manufacturing precision requirements compared to forming a single monolithic stacked structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the reliability and data storage capacity of semiconductor devices by enabling efficient electrical connections and preventing metal diffusion, thus enhancing the performance and stability of the semiconductor device.
Implementation Method 1
a diffusion barrier between the second contact plug and the source structure, extending along a portion of the lower surface of the source structure, and having conductivity
Data Source
AI summary
A semiconductor device includes: a first substrate structure including a first substrate, circuit devices, and first bonding pads; and a second substrate structure connected to the first substrate structure. The second substrate structure includes: a source structure; gate electrodes stacked and spaced apart from each other below the source structure in a first direction; first contact plugs electrically connected to the gate electrodes and extending in the first direction; a second contact plug extending in the first direction in an external side of the gate electrodes and electrically connected to the source structure through an upper end; a diffusion barrier between the second contact plug and the source structure, wherein a level of a lower end thereof is higher than a level of an uppermost surface of the gate electrodes; and second bonding pads below the gate electrodes and connected to the first bonding pads.