3D NAND Memory Array Layout for Direct Channel Coupling
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently forming vertically-stacked memory cells with reliable electrical connections and structural integrity, particularly in NAND architecture, which affects data retention and access performance.
Innovation Solution
A method involving 'gate-last' or 'replacement-gate' processing is employed to form vertically-stacked memory cells with alternating conductive and insulative tiers, using etching and deposition techniques to create channel openings, trenches, and form conductive lines for wordlines, ensuring direct electrical coupling and structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically-stacked memory cells are formed using conventional processing methods, then manufacturing complexity is reduced, but electrical connectivity and structural integrity deteriorate
Solution Approach 1:
The method performs preliminary actions by forming the conductor tier and insulative tiers before forming the channel-material strings. Etch-stop linings are deposited in advance to control subsequent etching processes, ensuring proper electrical connections are established before the memory cell structures are completed.
Solution Approach 2:
The memory array is segmented into multiple vertically-stacked memory blocks, each comprising alternating conductive and insulative tiers. This segmentation allows independent formation and optimization of each memory block, improving overall electrical connectivity while managing processing complexity through modular fabrication.
2Productivity
If vertically-stacked memory cells are formed with direct electrical coupling, then data access performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
Etch-stop linings serve as intermediary layers between the conductor tier and the memory block structures. These linings facilitate precise etching processes that create channel openings with accurate alignment, enabling direct electrical coupling between channel-material strings and conductor material while maintaining controllable manufacturing precision.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional vertically-stacked architecture. Memory cells are arranged in vertical tiers with alternating conductive and insulative layers, allowing direct electrical coupling along the vertical dimension while distributing manufacturing precision requirements across multiple fabrication steps.
3Stability of the object's composition
If etch-stop lining is deposited in trenches, then structural integrity is improved, but manufacturing steps increase
Solution Approach 1:
Etch-stop linings are deposited in advance during the tier formation process, before the channel openings are etched. This preliminary action ensures that the linings are already in place to control the etching process, preventing structural damage while integrating the step into the overall fabrication sequence.
Solution Approach 2:
The etch-stop linings serve multiple functions: they control etching depth and selectivity, provide structural support during subsequent processing steps, and define the boundaries of channel openings. This multi-functionality justifies the additional manufacturing step by consolidating multiple requirements into a single layer.
Data Source
AI summary
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier. Laterally-inner insulating material extends longitudinally-along the immediately-laterally-adjacent memory blocks laterally-inward of the laterally-outer insulative lining. An interface is between the laterally-outer insulative lining and the laterally-inner insulating material. Methods are also disclosed.