3D NAND Memory Device with Interconnect Disconnection Detection
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Solution Overview
Problem
NAND flash memory devices with three-dimensional structures face challenges in detecting defective memory areas due to disconnections, which can affect device operation and hinder high integration and large capacity performance.
Innovation Solution
A memory device with a row decoder module that includes a disconnection detection circuit and switch, capable of detecting broken wires through a series of operations involving voltage application and detection circuits, ensuring reliable communication between components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is employed to achieve high integration and large capacity, then storage capacity increases, but the difficulty of detecting defective memory areas due to disconnections increases
Solution Approach 1:
The memory device is divided into multiple blocks, and each block is further divided into multiple strings. The row decoder is segmented into multiple row decoders, each responsible for a specific block. This segmentation allows targeted detection and isolation of defective areas without affecting the entire memory device, enabling efficient defect management in high-capacity three-dimensional structures.
Solution Approach 2:
A disconnection detection circuit is introduced as an intermediary component between the row decoder and the memory strings. This circuit includes a detection switch and detection circuitry that can detect disconnections in the row decoder output lines without disrupting normal memory operations. The intermediary detection mechanism enables monitoring of connection integrity in the complex three-dimensional interconnect structure.
2Reliability
If disconnection detection capability is added to the row decoder, then reliability improves, but device complexity increases
Solution Approach 1:
The disconnection detection circuit is merged with the row decoder structure, sharing common components such as the selection gate lines and control logic. The detection switch is integrated into the existing row decoder output line structure, allowing defect detection functionality to be combined with the signal routing function. This merging approach adds reliability while minimizing the increase in overall device complexity.
Solution Approach 2:
The row decoder output lines serve dual functions: they carry control signals to the memory strings during normal operation and simultaneously serve as test paths for disconnection detection. The same physical infrastructure (interconnect lines, transistors) is utilized for both data/control transmission and defect detection, reducing the additional complexity burden.
3Reliability
If defect detection operations are performed frequently to ensure reliability, then operational reliability improves, but productivity decreases due to additional detection time
Solution Approach 1:
Disconnection detection is performed as a preliminary action during manufacturing or initialization, before the memory device is deployed for normal operations. The detection circuit identifies and isolates defective blocks and strings in advance, allowing them to be remapped or replaced without interfering with subsequent high-speed memory operations. This preliminary defect identification ensures reliability while maintaining productivity during actual use.
Solution Approach 2:
The memory device performs self-diagnosis through the disconnection detection circuit, automatically identifying and isolating defective areas without requiring external intervention or slowing down normal operations. The detection mechanism operates independently during idle cycles or initialization, allowing the memory to service its own reliability needs without impacting productivity during active data operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively identifies and isolates defective memory areas, preventing operational failures and maintaining the integrity of the memory device's performance, thereby supporting high integration and large capacity requirements.
Implementation Method 1
a disconnection detection circuit configured to detect a disconnection of the interconnect BLKSELn by applying a voltage to the interconnect BSNOD_SUP through the switch SW and detecting a voltage of the interconnect PBUSBS
Data Source
AI summary
According to one embodiment, a memory device includes a first block including a first memory string having a first transistor at an end, a second transistor having a first end connected to a gate of the first transistor, first interconnect connected to a gate of the second transistor, a block decoder connected to one end of the first interconnect, a third transistor having a first end connected to the other end of the first interconnect, and a power supply connected to a second end of the third transistor.