3D NAND Device with Discrete Charge Storage Regions
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Solution Overview
Problem
Current three-dimensional vertical NAND strings have limitations in density and manufacturing complexity, with existing methods providing only one bit per cell and involving time-consuming processes for forming active regions.
Innovation Solution
A method for creating monolithic three-dimensional NAND strings with vertically oriented semiconductor channels, multiple control gate electrodes, and discrete charge storage regions, using alternating layers of insulating and sacrificial materials, and forming tunnel and blocking dielectrics to enhance memory cell density and simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If repeated formation of sidewall spacers and etching of substrate is used to form active regions, then conical active region shape is achieved, but the process becomes time-consuming and complex
Solution Approach 1:
The patent extracts and removes the complex sidewall spacer formation steps from the manufacturing process. Instead of forming conical shapes through repeated spacer deposition and etching, the invention uses a simplified planar active region formation method that achieves the same functional result without the time-consuming intermediate steps.
Solution Approach 2:
The patent performs preliminary patterning of the active regions before transistor formation, establishing the final active region geometry in a single step rather than through iterative spacer formation. This preliminary action defines the active region boundaries upfront, eliminating subsequent complex shaping operations.
2Quantity of substance
If conventional NAND string structure is used, then one bit per cell is achieved, but memory density is limited
Solution Approach 1:
The patent transitions from planar memory cell layouts to three-dimensional vertically stacked transistor structures. By stacking multiple transistors vertically over a single active region, the invention achieves multiple bits per cell while maintaining a compact footprint, effectively utilizing the vertical dimension to increase storage density.
Solution Approach 2:
The patent implements nested transistor structures where multiple transistor channels are stacked vertically within a single active region footprint. Each transistor in the stack can store one bit, allowing multiple bits to be packed into the area traditionally occupied by a single planar transistor, thereby increasing bits per cell.
3Quantity of substance
If vertically stacked transistor structure is implemented, then multiple bits per cell is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the vertically stacked transistor structure into independently formable units using sacrificial layer techniques. Each transistor level can be formed and aligned separately through controlled etching and deposition processes, reducing the cumulative alignment error that would result from attempting to form all levels in a single complex step.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that facilitate precise alignment of vertically stacked transistors. These sacrificial layers serve as temporary alignment references during manufacturing, enabling accurate positioning of each transistor level relative to others, and are removed after serving their alignment function.
Data Source
AI summary
A method of making a monolithic three dimensional NAND string includes forming a stack of alternating layers of a first material and a second material, etching the stack to form a front side opening in the stack, selectively forming a plurality of discrete semiconductor, metal or silicide charge storage regions on portions of the second material layers exposed in the front side opening, forming a tunnel dielectric layer and semiconductor channel layer in the front side opening, etching the stack to form a back side opening in the stack, removing at least a portion of the second material layers through the back side opening to form back side recesses between the first material layers, forming a blocking dielectric in the back side recesses through the back side opening, and forming control gates over the blocking dielectric in the back side recesses through the back side opening.