3D NAND Divided Select Gates for Faster Erase and Transfer

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Solution Overview

Problem

As 3D-NAND memory devices migrate to higher capacity with increasing block size, they experience longer erasing and data transfer times and lower storage efficiency due to shared control gates across multiple memory cell strings.

Innovation Solution

The introduction of a divided block structure, where shared bottom select gates (BSGs) and top select gates (TSGs) are separated into sub-BSGs and sub-TSGs through dielectric trenches, allowing individual control of sub-blocks and reducing parasitic capacitance and coupling effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the block size is increased to achieve higher storage capacity, then the storage capacity is improved, but the erasing time and data transfer time are extended

Engineering Contradiction:

Improvestorage capacityVSAvoiderasing time and data transfer time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent divides a large memory block into multiple smaller sub-blocks, each with its own independent select gates. This segmentation allows individual sub-blocks to be accessed, erased, or transferred independently, reducing the time required for these operations while maintaining the total storage capacity of the original large block.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If the number of word line layers is increased to achieve higher density, then the storage density is improved, but the block size increases leading to lower storage efficiency

Engineering Contradiction:

Improvestorage densityVSAvoidstorage efficiency

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the memory structure into multiple sub-blocks with independent control, allowing efficient management of high-density storage. Each sub-block can be independently accessed and operated, improving storage efficiency despite the increased number of word line layers required for high density.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of control by adding independent select gates for each sub-block. This additional control dimension enables fine-grained access to sub-blocks within high-density structures, improving storage efficiency without reducing the number of word line layers needed for high density.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Device complexity

If shared select gates are used to control multiple memory cell strings, then the device complexity is reduced, but the parasitic capacitance and coupling effects increase

Engineering Contradiction:

Improvegate control structureVSAvoidparasitic capacitance and coupling effects

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the shared select gate structure into multiple independent select gates, each controlling a specific sub-block. This segmentation reduces parasitic capacitance and coupling effects by isolating the electrical fields of adjacent select gates, while the overall gate control structure remains relatively simple through systematic repetition of the segmented units.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20250024679A13D NAND memory device and method of forming the same

Publication Date: 2025.01.16 YANGTZE MEMORY TECH CO LTD

AI summary

In certain aspects, a method of erasing a memory device is disclosed. The memory device includes a bottom select gate (BSG) and a dielectric trench separating the BSG into a first sub-BSG and a second sub-BSG. A first voltage is applied to the first sub-BSG. A second voltage is applied to the second sub-BSG. The second voltage is different from the first voltage.