3D NAND Block Architecture Using Dummy Pillars Against Stack Lifting

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Solution Overview

Problem

In 3D NAND Flash storage devices, the increasing height of semiconductor pillars during manufacturing leads to defects such as the 'lifting' of the stack off the underlying substrate, resulting in defective wafers, which hampers the achievement of higher memory density.

Innovation Solution

The use of 'dummy' pillars etched deep into the silicon base substrate, combined with active channel pillars, and partially inset tungsten plugs to strengthen the connection between the stack and the substrate, thereby preventing the lifting of the conductive and insulating films and distributing stress effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the height of semiconductor pillars is increased to achieve higher memory density, then memory density is improved, but the stack lifts off the underlying substrate causing manufacturing defects

Engineering Contradiction:
Improvememory densityVSAvoidstack stability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

Dummy pillars are etched deep into the substrate before forming the complete stack structure. This preliminary action creates anchoring points that prevent subsequent lifting of the stack during manufacturing processes, allowing the use of taller semiconductor pillars for increased memory density without compromising stack stability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy pillars act as intermediary structures between the substrate and the conductive/insulating film stack. These intermediary elements provide mechanical support and stress distribution, enabling the tall stack to remain firmly attached to the substrate while maintaining the desired memory density.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If taller semiconductor pillars are used to increase memory capacity, then memory capacity is improved, but manufacturing defects increase due to stack lifting

Engineering Contradiction:
Improvememory capacityVSAvoiddefect rate
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The dummy pillars are formed during the preliminary stages of manufacturing, establishing a stable foundation before the complete stack is assembled. This preliminary structuring prevents manufacturing defects by ensuring the tall stack remains anchored throughout subsequent processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy pillars serve as intermediary support structures that mediate between the substrate and the tall stack, distributing mechanical stresses and preventing the stack from lifting off during manufacturing operations, thereby reducing defect rates.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If the vertical height of the memory array is increased, then memory density is improved, but stress distribution becomes problematic causing wafer defects

Engineering Contradiction:
Improvememory densityVSAvoidstress distribution
Core Design Contradiction:
Quantity of substanceVSStress or pressure

Solution Approach 1:

The support structure is segmented into multiple dummy pillars distributed across the substrate. This segmentation allows stress to be distributed across multiple discrete anchoring points rather than concentrated in a single location, enabling the support of taller memory arrays with improved stress management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dummy pillars act as intermediary stress-distribution elements, intercepting and dispersing mechanical stresses throughout the substrate-stack interface. This intermediary stress management enables the construction of taller memory arrays without compromising wafer integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240128207A1NAND flash block architecture enhancement to prevent block lifting
Publication Date: 2024.04.18 MICRON TECHNOLOGY INC
  • US20240128207A1 patent drawing
  • US20240128207A1 patent drawing
  • US20240128207A1 patent drawing

AI summary

Disclosed is a three-dimensional memory device. In one embodiment, a device is disclosed comprising a source plate; plugs fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.