3D NAND ECC Control Using Wordline-Specific Codeword Structures
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Solution Overview
Problem
Conventional error checking and correcting (ECC) solutions for NAND flash memory with a 3-dimensional architecture are ineffective due to non-uniform error bit distributions among wordlines, leading to over-configuration of parity bit length and reduced storage device performance.
Innovation Solution
A controller device and method that groups wordlines into groups with different codeword structures, allowing adaptive assignment of parity bit lengths based on the specific wordline group, thereby reducing over-configuration and improving error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC solutions with fixed parity bit length are used for 3D NAND flash memory, then error correction capability is provided, but over-configuration of parity bit length occurs leading to reduced storage device performance
Solution Approach 1:
The patent segments the wordlines into multiple groups (first wordline group and second wordline group) based on their error bit distribution characteristics. Each group is assigned a different codeword structure with appropriately tailored parity bit lengths, avoiding the over-configuration that occurs when a fixed parity bit length is applied to all wordlines.
Solution Approach 2:
The patent applies local quality by assigning different codeword structures with different parity bit lengths to different wordline groups according to their specific error characteristics. The first wordline group receives a first codeword structure while the second wordline group receives a second codeword structure, optimizing error correction resources locally rather than uniformly across all wordlines.
2Ease of operation
If uniform codeword structure is applied to all wordlines in 3D NAND flash memory, then ECC operation is simplified, but error correction efficiency is reduced due to non-uniform error bit distributions
Solution Approach 1:
The patent divides wordlines into distinct groups that require different codeword structures, segmenting the ECC operation to match the non-uniform error bit distributions across different wordline groups in 3D NAND flash memory.
Solution Approach 2:
The patent changes the parameters of the codeword structure (specifically the parity bit length) to match the error characteristics of different wordline groups, thereby optimizing error correction efficiency for each group's specific error distribution pattern.
Data Source
AI summary
A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.