3D NAND With Embedded DRAM for High-Speed I/O and Smaller Die Size
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Solution Overview
Problem
Conventional 3D memory devices face challenges with poor array efficiency, large die size, high cost, and slow program, erase, and read speeds due to peripheral circuits occupying a large area and thermal budget limitations, which hinder high input/output (I/O) speed and memory density.
Innovation Solution
The integration of on-chip embedded DRAM with high-speed advanced logic processing and 3D NAND memory formed on separate substrates, bonded together to form a non-monolithic 3D memory device, where peripheral circuits and embedded DRAM cells are fabricated using CMOS technology, enabling high-speed data storage and reduced chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If peripheral circuits are integrated on the same substrate as the memory array, then device functionality is complete, but die size becomes large and array efficiency deteriorates
Solution Approach 1:
The device is divided into two separate substrates: a first substrate containing the memory array and a second substrate containing the peripheral circuits and embedded DRAM. This segmentation allows each substrate to be optimized independently, reducing the overall die size while maintaining complete device functionality through vertical integration.
Solution Approach 2:
The invention transitions from a planar integration approach to a three-dimensional stacked architecture. By placing the peripheral circuits on a separate substrate and bonding it vertically to the memory array substrate, the solution utilizes the vertical dimension to achieve high integration without increasing the lateral die size.
2Adaptability or versatility
If peripheral circuits occupy large area on the same substrate, then all functions are available, but memory array efficiency decreases
Solution Approach 1:
By segregating the peripheral circuits from the memory array onto a separate substrate, the memory array area is maximized and not compromised by peripheral circuit occupancy. This segmentation enables the memory array to operate with higher efficiency while the peripheral circuits maintain all necessary functions on the bonded substrate.
3Ease of manufacture
If conventional planar process technology is used to scale memory cells, then manufacturing is straightforward, but memory density approaches an upper limit
Solution Approach 1:
The invention transitions from two-dimensional planar memory cell scaling to three-dimensional stacked architecture. By vertically stacking the memory array and peripheral circuits on separate substrates, memory density is dramatically increased without requiring further scaling of the planar process technology, thus maintaining manufacturing simplicity while achieving higher density.
4Reliability
If thermal budget limitations are considered in 3D memory devices, then device reliability is maintained, but I/O speed becomes slow
Solution Approach 1:
An embedded DRAM is integrated on the second substrate as an intermediary buffer between the memory array and external interfaces. This embedded DRAM enables high-speed I/O operations by handling data buffering and transfer operations, while the thermal budget limitations are managed through the separate substrate architecture that allows independent thermal management of each component.
Data Source
Figure 1A~1B
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AI summary
Three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. A 3D memory device (300) includes a first semiconductor structure (302) including a peripheral circuit (312), an array of embedded DRAM cells (314), and a first bonding layer (324) including a plurality of first bonding contacts (326). The 3D memory device also further includes a second semiconductor structure (304) including an array of 3D NAND memory strings (338) and a second bonding layer (328) including a plurality of second bonding contacts (330). The 3D memory device (300) further includes a bonding interface (306) between the first bonding layer (324) and the second bonding layer (328). The first bonding contacts (324) are in contact with the second bonding contacts (328) at the bonding interface (306).