3D-NAND Erase Circuit Mitigates Grown Bad Blocks
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Solution Overview
Problem
Existing 3D-NAND storage devices face structural limitations that lead to high electric stress during erase operations, resulting in word-line-memory-hole-shorts and permanent program failures due to the funnel-like shape of memory strings, causing storage device failures.
Innovation Solution
Implementing an erase circuit that terminates word line erase pulses at different times based on the location of memory cells along the memory channel and adapts durations and termination times based on temperature, to mitigate electric stress and reduce the occurrence of grown bad blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory strings are energized during program/erase operations, then memory cells can be programmed or erased, but high electric stress develops across the memory strings causing word-line-memory-hole-shorts
Solution Approach 1:
The patent segments the memory block into multiple zones along the memory channel (first zone, second zone, third zone) and applies different erase pulse durations to each zone. This segmentation allows targeted control of electric stress in different regions, preventing uniform high stress that causes word-line-memory-hole-shorts while maintaining erase functionality.
Solution Approach 2:
The patent implements local quality by assigning different erase pulse durations to different zones based on their specific characteristics. The first zone (closer to substrate) receives a first duration, the second zone receives a second duration, and the third zone receives a third duration. This localized approach optimizes erase effectiveness in each region while controlling electric stress to prevent shorts.
2Ease of operation
If uniform erase pulse duration is applied to all memory cells, then erase operation is simple to control, but electric stress is not uniformly managed leading to grown bad blocks
Solution Approach 1:
The patent transitions from static uniform erase control to dynamic adaptive erase control. The erase circuit dynamically adjusts pulse durations based on zone location and temperature feedback. Temperature sensors monitor real-time conditions and the control circuit modifies erase parameters accordingly, creating a dynamic system that adapts to changing thermal and electrical conditions to prevent grown bad blocks.
Solution Approach 2:
The patent implements feedback mechanisms through temperature sensors that monitor the memory block temperature during erase operations. The control circuit receives this temperature feedback and adjusts the erase pulse durations for different zones accordingly. This closed-loop feedback system ensures electric stress is managed within safe limits while maintaining erase effectiveness, preventing the formation of grown bad blocks.
Data Source
AI summary
Example techniques that mitigate against memory hole shorts during an erase operation for memory cells in a string include an example method in which, during an erase operation, erase pulses are applied to the word lines of the memory string and terminated at different times based. In some instances, the erase pulses applied to the word lines of the memory string are terminated based on the temperature of the memory cells of the memory string. In further implementations, the erase pulses applied to the word lines of the memory string are boosted for different times depending on the location of the word line along the memory string during the erase operation.