3D NAND Erase Timing Control for Temperature-Driven Over-Erase
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Solution Overview
Problem
Nonvolatile memory devices face issues with memory cells being over-erased due to variations in operating temperature during erase operations, particularly in three-dimensional structures like vertical NAND memory devices.
Innovation Solution
A method and device that adjusts the erase execution time interval of word-lines in nonvolatile memory devices based on sensed operating temperature, dividing word-lines into groups and applying erase voltages and inhibit voltages at different time points to prevent over-erasure, using a digital temperature sensor and control circuit to manage erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operation is performed on nonvolatile memory device, then memory cells are erased, but memory cells may be over-erased due to operating temperature variations
Solution Approach 1:
The patent applies dynamics by making the erase execution time interval adjustable based on operating temperature. The control circuit dynamically modifies the time interval for applying erase voltages to different word-line groups according to the detected temperature, allowing the erase operation to adapt to temperature variations and prevent over-erasure while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of erase execution time interval based on operating temperature. The control circuit detects temperature and adjusts the time interval parameter for applying erase voltages to different word-line groups, thereby controlling erase distribution precision and preventing over-erasure across varying temperature conditions.
2Productivity
If erase voltage is applied to all word-lines simultaneously, then erase operation is completed quickly, but temperature variations cause over-erasure in certain regions
Solution Approach 1:
The patent segments the word-lines into multiple groups (first, second, and third word-line groups) and applies erase voltages to each group at different time intervals based on temperature. This segmentation allows the erase operation to maintain speed while achieving uniform erase distribution across different temperature conditions by controlling each group separately.
Solution Approach 2:
The patent implements periodic action by applying erase voltages to different word-line groups at different time intervals. The control circuit sequentially applies erase voltages to each group with temperature-dependent timing, enabling both efficient erase completion and uniform erase distribution across the memory device.
3Manufacturing precision
If erase execution time interval is increased to prevent over-erasure, then erase distribution improves, but erase operation time increases
Solution Approach 1:
The patent uses dynamics to adjust the erase execution time interval based on actual operating temperature conditions. Rather than using a fixed increased time interval, the control circuit dynamically sets appropriate time intervals for different word-line groups according to temperature, achieving precise erase distribution control without unnecessary time delays.
Solution Approach 2:
The patent changes the erase execution time interval parameter adaptively based on temperature detection. The control circuit modifies this parameter for different word-line groups according to operating temperature, optimizing the balance between erase distribution precision and operation time by applying appropriate timing only when needed.
Data Source
AI summary
There is provided a method of operating a nonvolatile memory device that includes a plurality of memory blocks, each of the plurality of memory blocks including a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor which are connected in series and arranged in a vertical direction between each of a plurality of bit-lines and a common source line on and/or in a substrate, the method comprising: receiving an erase command and a block address designating a target memory block among the plurality of memory blocks; sensing an operating temperature of the nonvolatile memory device; and adjusting an erase execution time interval of each of word-lines of the target memory block, respectively, based on the sensed operating temperature, wherein the vertical direction is perpendicular to an upper surface of the substrate.