3D NAND Erase Voltage Control for Temperature Consistency
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in achieving consistent erase speed across varying operating temperatures due to temperature-dependent gate-induced drain leakage (GIDL) current and parasitic leakage currents during the erase operation of NAND strings.
Innovation Solution
Implementing a temperature-dependent GIDL erase voltage and regulating the erase voltage to maintain consistent GIDL current, independent of temperature, while mitigating parasitic leakage currents through advanced control circuitry and voltage management systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a fixed erase voltage is applied to NAND strings, then the erase operation can be performed with simple voltage control, but the erase speed becomes inconsistent across varying operating temperatures due to temperature-dependent GIDL current
Solution Approach 1:
The patent implements dynamic voltage adjustment by applying different erase voltages to the drain side select transistor control gate based on detected operating temperature. The voltage magnitude is dynamically adapted: higher voltages at lower temperatures and lower voltages at higher temperatures, transforming a static voltage control system into a dynamic one that responds to temperature conditions to maintain consistent erase performance
Solution Approach 2:
The patent changes the voltage parameter of the erase operation based on temperature conditions. By adjusting the voltage magnitude applied to the control gate according to the operating temperature range, the system compensates for temperature-dependent GIDL current variations, ensuring reliable erase speed across different thermal environments
2Productivity
If higher erase voltages are applied to compensate for low temperature GIDL current, then erase speed can be maintained at low temperatures, but parasitic leakage currents increase and reliability decreases
Solution Approach 1:
The patent applies different voltage levels to different operational conditions rather than using a uniform high voltage. By detecting the specific temperature condition and applying an appropriately tailored voltage magnitude, the system provides just enough voltage to achieve reliable erase at each temperature point, avoiding the excessive voltage that would cause parasitic leakage while ensuring sufficient erase speed
Solution Approach 2:
The patent incorporates temperature detection and uses this feedback to adjust the erase voltage magnitude. The system continuously monitors operating temperature and adapts the voltage applied to the control gate accordingly, creating a closed-loop control system that prevents both insufficient erase at low temperatures and excessive voltage-induced leakage at high temperatures
3Reliability
If temperature-dependent erase voltage is implemented, then erase speed consistency across temperature ranges is improved, but device complexity increases due to additional control circuitry
Solution Approach 1:
The patent segments the temperature operating range into distinct ranges and assigns specific voltage magnitudes to each range. The temperature detection circuit identifies which range the current operation falls into, and the control system selects the appropriate pre-determined voltage level. This segmentation approach simplifies the control logic compared to continuous analog adjustment while still achieving effective temperature compensation
Solution Approach 2:
The patent changes the voltage parameter based on detected temperature conditions, implementing a practical balance between complexity and performance. By using discrete voltage levels corresponding to temperature ranges rather than continuous adjustment, the system achieves reliable erase speed consistency while keeping the control circuitry manageable and the implementation feasible
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent erase speed and efficiency across the operating temperature range by adjusting erase voltages and currents, thereby improving the reliability and performance of NAND string erase operations.
Implementation Method 1
Another approach to erasing memory cells is to generate gate induced drain leakage (GIDL) current to charge up the NAND string channel
Data Source
AI summary
An apparatus for erasing non-volatile storage elements in a non-volatile memory system is disclosed. The apparatus has consistent speed in gate induced drain leakage (GIDL) erase across the operating temperature of the memory system. In one aspect, a voltage source outputs an erase voltage to NAND strings. The NAND strings may draw a GIDL erase current in response to the erase voltage. The amount of GIDL erase current for a given erase voltage is highly temperature dependent. The GIDL erase current may be sampled, and the erase voltage regulated based on the GIDL erase current. Therefore, the GIDL erase current, as well as erase speed, may be kept uniform across operating temperatures.