3D NAND Source Line Etch Stop for Monolithic Channel Pillars
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Solution Overview
Problem
Current three-dimensional NAND flash memory arrays face challenges in maintaining efficient current flow and reducing voltage loss due to defects and dimensional offsets in the vertical stacking of memory cells, which affects the reliability and performance of the memory devices.
Innovation Solution
The use of a conductive source line made of metallic silicide, such as tungsten silicide, as an etch stop material allows for the formation of a monolithic pillar of semiconductor material without discontinuities, reducing the impact of defects and dimensional offsets, and enabling a more uniform and efficient channel for the NAND string.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple high-temperature steps and patterned select gates are used in fabrication, then select gate functionality is achieved, but fabrication complexity and processing time increase
Solution Approach 1:
The patent removes the patterned select gate structure entirely from the fabrication process. Instead of forming select gates through multiple high-temperature steps and patterning operations, the invention uses a continuous barrier layer approach where the barrier layer itself defines the select gate regions through its spatial distribution, eliminating the need for complex select gate fabrication while maintaining the necessary electrical isolation and control functions
Solution Approach 2:
The barrier layer serves multiple functions simultaneously: it acts as a diffusion barrier, defines select gate regions, provides electrical isolation, and serves as a structural template for subsequent layer formation. This multi-functionality consolidates what would otherwise require separate select gate fabrication steps into a single integrated process element
2Productivity
If conventional fabrication processes are used, then manufacturing steps are completed, but dimensional offsets and defects occur in vertical stacking
Solution Approach 1:
The barrier layer is formed early in the fabrication sequence, before subsequent layers are deposited. This preliminary formation establishes a precise spatial reference that guides the alignment of all subsequent layers, preventing dimensional offsets from accumulating during the vertical stacking process. The barrier layer's position and thickness are controlled beforehand to ensure accurate registration of overlying structures
Solution Approach 2:
The barrier layer acts as an intermediary reference structure between the substrate and the upper layers. It provides a stable, precisely-defined interface that mediates the alignment relationship between lower and upper portions of the vertical stack, ensuring that dimensional offsets are minimized and defects are reduced through improved registration accuracy
3Quantity of substance
If vertical stacking of memory cells is implemented, then three-dimensional array density is increased, but current flow efficiency decreases due to defects and dimensional offsets
Solution Approach 1:
The continuous barrier layer creates a hydraulically-equivalent electrical isolation system that prevents defect propagation through the vertical stack. By providing uninterrupted barrier coverage, it ensures that current flow paths remain clean and efficient, blocking the spread of electrical defects that would otherwise degrade current flow efficiency in high-density vertical arrays
Solution Approach 2:
The barrier layer provides localized quality enhancement at critical interfaces within the vertical stack. By concentrating barrier properties at specific locations where defects are most likely to occur, it selectively improves current flow efficiency in the most vulnerable regions while maintaining the overall high-density vertical architecture
Data Source
AI summary
A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.