3D NAND Memory Etching Control via Intermediate Layer Stoppers
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Solution Overview
Problem
In three-dimensional semiconductor memory devices, achieving high shape and dimensional controllability during the formation of memory holes or slits in stacked bodies with multiple layers is challenging, particularly when the central axes of holes in different stacked portions are misaligned, leading to reduced yield and potential degradation of device performance.
Innovation Solution
The introduction of enlarged portions in the intermediate layer, which act as stoppers, allows for reliable etching control and prevents memory holes or slits from extending into lower stacked portions, even when central axes are misaligned, enabling divided-stage formation without enlarging the memory cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a memory hole or slit is formed using RIE method in a stacked body with multiple electrode layers and insulating layers, then the three-dimensional memory structure can be created, but higher shape controllability and dimensional controllability are required for the etching operation as the number of layers increases
Solution Approach 1:
The stacked body is divided into multiple stacked portions (first stacked portion, second stacked portion, etc.) separated by intermediate layers. This segmentation allows the etching process to be controlled in stages, with each intermediate layer acting as a barrier that prevents etching from penetrating too deeply, thereby maintaining shape and dimensional controllability even as the total number of layers increases.
Solution Approach 2:
Intermediate layers are introduced as intermediary structures between the stacked portions. These intermediate layers serve as etch stoppers that mediate the etching process, preventing direct through-etching and allowing precise control over the depth and shape of memory holes or slits in multi-layer structures.
2Productivity
If the central axes of holes in different stacked portions are misaligned, then the manufacturing process becomes more challenging, but this misalignment leads to reduced yield and potential degradation of device performance
Solution Approach 1:
Intermediate layers are provided beforehand between stacked portions to cushion or compensate for potential misalignment issues. These layers act as a buffer zone that prevents complete through-etching even when central axes are misaligned, thereby protecting against yield reduction and performance degradation before they can occur.
Solution Approach 2:
The intermediate layer serves as an intermediary structure that accommodates misalignment between stacked portions. By providing this intermediate barrier, the system can tolerate certain degrees of axis misalignment without compromising the overall device functionality or manufacturing yield.
3Quantity of substance
If the number of layers in the stacked body increases to enhance memory capacity, then the storage capacity increases, but higher shape controllability and dimensional controllability are required for the etching operation
Solution Approach 1:
The stacked body is segmented into multiple portions separated by intermediate layers, allowing the memory structure to scale in capacity (number of layers) while maintaining etching controllability. Each segment can be independently controlled during the etching process.
Solution Approach 2:
Intermediate layers are introduced as mediators that enable the stacking of multiple layers for increased capacity while preventing uncontrolled etching penetration. These intermediaries maintain the structural integrity and etching controllability of high-capacity multi-layer structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances yield and shape/dimensional controllability, preventing degradation and allowing for capacity enlargement, cost reduction, and speed improvement in memory device manufacturing.
Implementation Method 1
a memory hole or a slit is formed using a reactive ion etching (RIE) method
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a first stacked portion, a second stacked portion and an intermediate layer, the first stacked portion and the second stacked portion including a plurality of electrode layers and a plurality of insulating layers, the intermediate layer provided between the first stacked portion and the second stacked portion; a column including a semiconductor film and a charge storage film; and an insulating part provided in the stacked body. The column has a first enlarged portion. The insulating part has a second enlarged portion surrounded by the intermediate layer, the second enlarged portion has a larger width than a width of the portion of the insulating part in the first stacked portion and the second stacked portion.