3D NAND Extension Region Layout for Higher Density Gate Stacks
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Solution Overview
Problem
The integration density of two-dimensional semiconductor devices is limited by the high cost and complexity of fine pattern forming technologies, necessitating the development of three-dimensional semiconductor devices to enhance performance and reduce costs.
Innovation Solution
A semiconductor device with a mold structure featuring alternately stacked insulating patterns and gate electrodes, along with a channel structure that intersects the gate electrodes, and extension gate cutting regions to selectively remove insulating patterns, allowing for increased integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pattern forming technology is used to increase integration density of 2D semiconductor devices, then integration density is improved, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar device architecture to three-dimensional stacked architecture by forming multiple layers of insulating patterns and gate electrodes vertically. This dimensional change allows integration density to increase without requiring finer lateral patterning, thereby avoiding the associated cost and complexity increases.
Solution Approach 2:
The device is segmented into multiple functional layers stacked vertically, including alternating insulating patterns and gate electrodes. This segmentation allows each layer to be formed using standard patterning processes while achieving higher overall integration density through the stacked configuration.
2Quantity of substance
If more gate electrodes and insulating patterns are stacked to increase integration density, then device functionality is improved, but fabrication process complexity increases
Solution Approach 1:
Multiple insulating patterns and gate electrodes are formed in a predetermined stacked sequence using sequential deposition and patterning steps. The preliminary formation of each layer with proper alignment markers and spacing facilitates subsequent layer formation, making the multi-layer fabrication process more manageable despite the increased number of steps.
Solution Approach 2:
The alternating insulating patterns and gate electrodes serve multiple functions: electrical isolation, mechanical support, and active device formation. This multi-functionality reduces the need for additional specialized layers, simplifying the overall fabrication process while maintaining high integration density.
3Quantity of substance
If alternating insulating patterns and gate electrodes are formed in multiple layers, then integration density increases, but material cost and processing steps increase
Solution Approach 1:
The formation of insulating patterns and gate electrodes is merged into a single alternating deposition and patterning cycle. Multiple layers are built up through repeated iterations of the same basic process steps rather than using entirely different processes for each layer, improving fabrication efficiency while achieving high integration density.
Solution Approach 2:
The patent varies parameters such as the thickness, material composition, and lateral dimensions of insulating patterns and gate electrodes across different layers to optimize device performance. These parameter changes are achieved through controlled deposition and patterning conditions rather than adding new process steps, maintaining fabrication efficiency.
Data Source
AI summary
A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.