3D NAND Channel Doping via Fixed Charges for Read Margin
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Solution Overview
Problem
3-dimensional NAND flash memory devices face a challenge in maintaining a high degree of integration and achieving high-speed, low-power driving while ensuring a sufficient sensing margin, as increasing the number of cell transistors reduces the read current and sensing margin, leading to decreased cell integration.
Innovation Solution
The introduction of a fixed charge region at the interface of the interlayer insulating layer and information storing layer, or within the information storing layer between control gates, induces an electrically doped region on the semiconductor channel layer, reducing channel resistance and enhancing read current. This is achieved through hydrogen bonding and fringing field-induced charges, with a work function control layer and specific insulating layer materials like SiO2 and HfO2, and a method involving incremental pulse programming to form and eliminate these charge regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of cell transistors is increased to improve the degree of integration, then the degree of integration is improved, but the resistance of the semiconductor channel is increased and the sensing margin for read operation is reduced
Solution Approach 1:
The patent introduces a fixed charge region in the information storing layer to change the electrical parameters of the semiconductor channel. By controlling the charge state (programmed charge or erased state) in the information storing layer, the patent dynamically adjusts the channel conductivity to maintain sensing margin even with increased cell transistor count
Solution Approach 2:
The information storing layer acts as an intermediary between the control gates and the semiconductor channel. It mediates the electrical interaction by storing charges that indirectly modulate the channel resistance, allowing for better control of the sensing characteristics without directly altering the channel structure
2Reliability
If the size of a detection amplifier is increased to secure the sensing margin, then the sensing margin is secured, but the degree of cell integration decreases
Solution Approach 1:
Instead of increasing amplifier size, the patent changes the channel resistance parameter through fixed charge region control. This allows maintaining sensing margin with smaller amplifiers by pre-optimizing the channel electrical characteristics through charge state management in the information storing layer
3Quantity of substance
If the number of memory cells is increased to improve cell integration, then the degree of integration is improved, but the read current decreases leading to reduced sensing margin
Solution Approach 1:
The patent dynamically changes the channel conductivity parameter by controlling the charge state in the information storing layer. During read operations, the channel can be programmed to a low-resistance state to maintain sufficient read current even as the number of series-connected cells increases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves read current, enabling high-speed and low-power operation with reduced read errors, thereby enhancing the degree of integration and reliability of the 3-dimensional NAND flash memory device.
Implementation Method 1
a fixed charge region disposed at an interface of the interlayer insulating layer and the information storing layer or in a portion of the information storing layer between the control gates in the first direction; and an electrically doped region which is induced by the fixed charge region
Implementation Method 2
the fixed charge region disposed at the interface of the interlayer insulating layer and the information storing layer may include a dangling bond of hydrogen molecules formed by a reaction of hydrogen bonding between hydrogen ions (W) and the interlayer insulating layer at the interface
Implementation Method 3
the fixed charge region disposed in the portion of the information storing layer between the control gates may be charged by fixed charges accumulated by a fringing field induced between the control gates and the semiconductor channel layer
Data Source
AI summary
A 3-dimensional flash memory device and methods of fabricating and driving the same are provided. The device includes: a channel layer extending over a substrate in a first direction perpendicular to a surface of the substrate; an information storing layer extending along a sidewall of the channel layer in the first direction; control gates each surrounding the channel layer, with the information storing layer between the channel layer and the control gates; an insulating layer being between the control gates in the first direction and separating the control gates from each other; a fixed charge region disposed at an interface of the insulating layer and the information storing layer or in a portion of the information storing layer between the control gates in the first direction; and a doped region induced by the fixed charge region and disposed at a surface of the channel layer facing the fixed charge region.